Attention is currently required from: Nico Huber, Arthur Heymans, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 )
Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ......................................................................
Patch Set 2:
(4 comments)
Patchset:
PS2:
It looks functionally different on everything but fam14
I don't exactly understand what is different? Could you elaborate?
File src/northbridge/amd/agesa/family15tn/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/c8bd81b8_94a87066 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
This is gone?
Yes it is gone, we would need to support at least ~256GB of DRAM memory to have any other value than 0 in this register. Although CONFIG_CPU_ADDR_BITS is 48 (for virtual address space) this register describes only real DRAM in the system. I made a simplification based on reasonable conclusion that such an old system's mobile memory controller cannot support more than 16GB or 32GB of DRAM.
File src/northbridge/amd/agesa/family16kb/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/025c3a63_2fb67325 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
This is gone?
As above.
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/22392ad1_36b8dc58 PS2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
this is gone?
As above