coreboot-gerrit May 2021

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Change in coreboot[master]: sb/intel/common: Fix platform_is_resuming()
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52930 to look at the new patch set (#2). Change subject: sb/intel/common: Fix platform_is_resuming() ...................................................................... sb/intel/common: Fix platform_is_resuming() platform_is_resuming() was using the wrong register (… [View More]

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Change in coreboot[master]: [TOTEST]sb/intel/common: Move sleep type clearing into cbmem init
by Arthur Heymans (Code Review) 05 May '21

05 May '21

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52931 ) Change subject: [TOTEST]sb/intel/common: Move sleep type clearing into cbmem init ...................................................................... Abandoned Not worth changing -- To view, visit https://review.coreboot.org/c/coreboot/+/52931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-… [View More]

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Change in coreboot[master]: nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52787 ) Change subject: nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE ...................................................................... nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> … [View More]Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/beltino/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc 10 files changed, 4 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 9b990ce..b1b2f45 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index f0fcff0..6f072fe 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -20,7 +20,6 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS select GBB_FLAG_DISABLE_LID_SHUTDOWN diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e12aa15..77edc30 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -4,7 +4,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +verstage-y += chromeos.c ramstage-y += lan.c smm-y += variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 9e60500..c69f7c8 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -4,4 +4,4 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +verstage-y += chromeos.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 06883e4..cd3e27c 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -16,7 +16,6 @@ config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE config CBFS_SIZE hex diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e3f9aec..61c201a 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -14,7 +14,6 @@ bool "Start verstage in bootblock" default y select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE help Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 484b694..2af4424 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -17,8 +17,6 @@ config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 0d58704..4fe5dd173 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -14,7 +14,6 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE # CPU is reset without platform/TPM during romstage select TPM_STARTUP_IGNORE_POSTINIT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 215560f..501ca9f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -21,7 +21,6 @@ bool "Start verstage in bootblock" default y select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE help Sandy Bridge can either start verstage in a separate stage right after the bootblock has run or it can start it diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 9ffd764..2923035 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,10 +41,10 @@ romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c +verstage-y += lp_gpio.c endif -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c +verstage-y += pmutil.c CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include -- To view, visit https://review.coreboot.org/c/coreboot/+/52787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Gerrit-Change-Number: 52787 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52790 ) Change subject: sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP ...................................................................... sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was using the lp gpio code instead of the southbridge/intel/common code in verstage. Change-Id: … [View More]I775d3dc3540fbd8a939701d873183dd016e24ba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index adacc25..1fc3a63 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,6 +27,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f980a65..9ffd764 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,10 +41,10 @@ romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include -- To view, visit https://review.coreboot.org/c/coreboot/+/52790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4 Gerrit-Change-Number: 52790 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: soc/mediatek/mt8192: devapc: update domain remap setting
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52705 ) Change subject: soc/mediatek/mt8192: devapc: update domain remap setting ...................................................................... soc/mediatek/mt8192: devapc: update domain remap setting Update domain remap setting to prevent DSP (domain 4) from accessing registers. Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> Reviewed-on:… [View More] https://review.coreboot.org/c/coreboot/+/52705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8192/include/soc/devapc.h 2 files changed, 54 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index e854727..1fdc519 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -19,29 +19,33 @@ /* * Domain Remap: TINYSYS to non-EMI (3-bit to 4-bit) - * 1. SCP from 3 to 3 - * 2. others from XXX to 15 + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 */ SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3, - FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_4, FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15); /* * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit) - * 1. From domain 0 ~ 3 to domain 0 ~ 3 - * 2. others from XXX to domain 0 + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1, 2, 4 to domain 1 (forbidden for all) + * 3. From domain 3 to domain 3 + * 4. others from XXX to domain 0 */ SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), TWO_BIT_DOM_REMAP_0, MAS_DOMAIN_0, TWO_BIT_DOM_REMAP_1, MAS_DOMAIN_1, - TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_2, - TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3); + TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1, + TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3, + TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1); } @@ -49,20 +53,48 @@ { /* Domain */ SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2); + + /* + * Domain Remap: CONNSYS slave domain remap (4-bit to 2-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1 ~ 4 to domain 1 (forbidden for all) + * 3. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_1_0), + TWO_BIT_DOM_REMAP_0, MAS_DOMAIN_0, + TWO_BIT_DOM_REMAP_1, MAS_DOMAIN_1, + TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1, + TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_1, + TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1); + + /* + * Domain Remap: TINYSYS slave domain remap (4-bit to 3-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1 ~ 4 to domain 1 (forbidden for all) + * 3. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + THREE_BIT_DOM_REMAP_0, MAS_DOMAIN_0, + THREE_BIT_DOM_REMAP_1, MAS_DOMAIN_1, + THREE_BIT_DOM_REMAP_2, MAS_DOMAIN_1, + THREE_BIT_DOM_REMAP_3, MAS_DOMAIN_1, + THREE_BIT_DOM_REMAP_4, MAS_DOMAIN_1); } static void fmem_master_init(uintptr_t base) { - /* Domain Remap: TINYSYS to EMI (3-bit to 4-bit) - * 1. SCP from 3 to 3 - * 2. others from XXX to 15 + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 */ SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3, - FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15, + FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_4, FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15, FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15); diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h index e79acfa..921f36e 100644 --- a/src/soc/mediatek/mt8192/include/soc/devapc.h +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -68,9 +68,16 @@ DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_6, 27, 24) DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_7, 31, 28) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_0, 2, 0) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_1, 5, 3) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_2, 8, 6) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_3, 11, 9) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_4, 14, 12) + +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) #endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Gerrit-Change-Number: 52705 Gerrit-PatchSet: 5 Gerrit-Owner: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: tests/lib/crc_byte-test: Fix incorrect variable types
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52708 ) Change subject: tests/lib/crc_byte-test: Fix incorrect variable types ...................................................................... tests/lib/crc_byte-test: Fix incorrect variable types Some crc16_byte() and crc32_byte() tests had uint8_t instead of uint16_t or uint32_t. That caused CRC values to be truncated and made tests incorrect. Also fix incorrect pre-calculated CRC values and change … [View More]test buffer name to more the accurate. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I61ee029a6950a8dfeb54520b634eaf4ed6bac576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52708 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/crc_byte-test.c 1 file changed, 23 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/lib/crc_byte-test.c b/tests/lib/crc_byte-test.c index d7c9e10..12934bc 100644 --- a/tests/lib/crc_byte-test.c +++ b/tests/lib/crc_byte-test.c @@ -3,7 +3,7 @@ #include <tests/test.h> #include <crc_byte.h> -static const uint8_t test_data_u8[] = { +static const uint8_t test_data_bytes[] = { 0x2f, 0x8f, 0x2d, 0x06, 0xc2, 0x11, 0x0c, 0xaf, 0xd7, 0x4b, 0x48, 0x71, 0xce, 0x3c, 0xfe, 0x29, 0x90, 0xf6, 0x33, 0x6d, 0x79, 0x23, 0x9d, 0x84, @@ -37,10 +37,10 @@ 0xf5, 0x45, 0x05, 0x0d, 0x3d, 0x62, 0xb9, 0x00, 0x7b, 0x1e, 0xe8, 0xb5, 0x97, 0x6e, 0xa8, 0xf3, }; -static const size_t test_data_u8_sz = ARRAY_SIZE(test_data_u8); +static const size_t test_data_bytes_sz = ARRAY_SIZE(test_data_bytes); static const uint8_t test_data_crc7_checksum = 0x30; -static const uint16_t test_data_crc16_checksum = 0x63; -static const uint32_t test_data_crc32_checksum = 0x93; +static const uint16_t test_data_crc16_checksum = 0x1263; +static const uint32_t test_data_crc32_checksum = 0xc7f52a93; static void test_crc7_byte_zeros(void **state) { @@ -106,9 +106,10 @@ assert_int_not_equal(crc_value_1, crc_value_2); } +/* This test uses CRC() macro to check if it works correctly with provided crc function */ static void test_crc7_byte_static_data(void **state) { - uint8_t crc_value = CRC(test_data_u8, test_data_u8_sz, crc7_byte); + uint8_t crc_value = CRC(test_data_bytes, test_data_bytes_sz, crc7_byte); assert_int_equal(test_data_crc7_checksum, crc_value); @@ -146,8 +147,8 @@ static void test_crc16_byte_repeat_stream(void **state) { - uint8_t crc_value_1 = 0u; - uint8_t crc_value_2 = 0u; + uint16_t crc_value_1 = 0u; + uint16_t crc_value_2 = 0u; const size_t iterations = 17777; /* Calculate CRC16 twice for the same data and expect the same result. @@ -167,8 +168,8 @@ static void test_crc16_byte_single_bit_difference(void **state) { - uint8_t crc_value_1 = 0u; - uint8_t crc_value_2 = 0u; + uint16_t crc_value_1 = 0u; + uint16_t crc_value_2 = 0u; for (size_t i = 0; i < 2000; ++i) { crc_value_1 = crc16_byte(crc_value_1, (i % 128) << 1); @@ -181,9 +182,10 @@ assert_int_not_equal(crc_value_1, crc_value_2); } +/* This test uses CRC() macro to check if it works correctly with provided crc function */ static void test_crc16_byte_static_data(void **state) { - uint8_t crc_value = CRC(test_data_u8, test_data_u8_sz, crc16_byte); + uint16_t crc_value = CRC(test_data_bytes, test_data_bytes_sz, crc16_byte); assert_int_equal(test_data_crc16_checksum, crc_value); @@ -196,7 +198,7 @@ static void test_crc32_byte_zeros(void **state) { - uint16_t crc_value = 0u; + uint32_t crc_value = 0u; /* Expect zero as crc value after calculating it for single zero byte */ crc_value = crc32_byte(crc_value, 0); @@ -211,20 +213,20 @@ static void test_crc32_same_data_twice_different_value(void **state) { - uint16_t crc_value = 0u; + uint32_t crc_value = 0u; /* Expect value to change after feeding crc function with the same byte twice. */ crc_value = crc32_byte(crc_value, 0xDF); - assert_int_equal(0xf654, crc_value); + assert_int_equal(0x29d4f654, crc_value); crc_value = crc32_byte(crc_value, 0xDF); - assert_int_equal(0xa254, crc_value); + assert_int_equal(0x47c8e4bb, crc_value); } static void test_crc32_byte_repeat_stream(void **state) { - uint8_t crc_value_1 = 0u; - uint8_t crc_value_2 = 0u; + uint32_t crc_value_1 = 0u; + uint32_t crc_value_2 = 0u; const size_t iterations = 8935; /* Calculate CRC16 twice for the same data and expect the same result. @@ -244,8 +246,8 @@ static void test_crc32_byte_single_bit_difference(void **state) { - uint8_t crc_value_1 = 0u; - uint8_t crc_value_2 = 0u; + uint32_t crc_value_1 = 0u; + uint32_t crc_value_2 = 0u; for (size_t i = 0; i < 1338; ++i) { crc_value_1 = crc32_byte(crc_value_1, (i % 128) << 1); @@ -258,15 +260,16 @@ assert_int_not_equal(crc_value_1, crc_value_2); } +/* This test uses CRC() macro to check if it works correctly with provided crc function */ static void test_crc32_byte_static_data(void **state) { - uint8_t crc_value = CRC(test_data_u8, test_data_u8_sz, crc32_byte); + uint32_t crc_value = CRC(test_data_bytes, test_data_bytes_sz, crc32_byte); assert_int_equal(test_data_crc32_checksum, crc_value); /* Calculating CRC of data with its CRC should yield zero if data and/or checksum is correct */ - for (int i = 0; i < 4; ++i) + for (int i = 3; i >= 0; --i) crc_value = crc32_byte(crc_value, (test_data_crc32_checksum >> 8 * i) & 0xFF); assert_int_equal(0, crc_value); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61ee029a6950a8dfeb54520b634eaf4ed6bac576 Gerrit-Change-Number: 52708 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: tests: enable code coverage for unit tests
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52444 ) Change subject: tests: enable code coverage for unit tests ...................................................................... tests: enable code coverage for unit tests Add a new `coverage-unit-tests` make target that builds the unit tests for code coverage, runs the tests, and generates a coverage report. Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com> Change-Id: … [View More]I6ea780ee9e246c0bb8c35b8e0de4252431dabbff Reviewed-on: https://review.coreboot.org/c/coreboot/+/52444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/Makefile.inc 1 file changed, 16 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index fd3cd9f..44e3c69 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -154,6 +154,15 @@ rm -f $(testobj)/junit-$(subst /,_,$^).xml $(testobj)/$(subst /,_,$^).failed -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed +.PHONY: coverage-unit-tests + +coverage-unit-tests: TEST_CFLAGS += --coverage +coverage-unit-tests: TEST_LDFLAGS += --coverage +coverage-unit-tests: clean-unit-tests unit-tests + lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '*/$(testobj)/*' + genhtml -q -o build/tests/coverage_rpt -t "coreboot unit tests" \ + -s $(testobj)/tests.info + unit-tests: build-unit-tests run-unit-tests build-unit-tests: $(test-bins) @@ -185,9 +194,11 @@ help-unit-tests help:: @echo '*** coreboot unit-tests targets ***' - @echo ' unit-tests - Run all unit-tests from tests/' - @echo ' clean-unit-tests - Remove unit-tests build artifacts' - @echo ' list-unit-tests - List all unit-tests' - @echo ' <unit-test> - Build and run single unit-test' - @echo ' clean-<unit-test> - Remove single unit-test build artifacts' + @echo ' unit-tests - Run all unit-tests from tests/' + @echo ' clean-unit-tests - Remove unit-tests build artifacts' + @echo ' list-unit-tests - List all unit-tests' + @echo ' <unit-test> - Build and run single unit-test' + @echo ' clean-<unit-test> - Remove single unit-test build artifacts' + @echo ' coverage-unit-tests - Build unit tests for code coverage and' + @echo ' generate a code coverage report' @echo -- To view, visit https://review.coreboot.org/c/coreboot/+/52444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ea780ee9e246c0bb8c35b8e0de4252431dabbff Gerrit-Change-Number: 52444 Gerrit-PatchSet: 5 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: drivers/genesyslogic/gl9755: Disable debug mode to enable circuit pro...
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51000 ) Change subject: drivers/genesyslogic/gl9755: Disable debug mode to enable circuit protections ...................................................................... drivers/genesyslogic/gl9755: Disable debug mode to enable circuit protections In order for short circuit protection and over current protection to work, the debug mode needs to be turned off. BUG=b:185749961 TEST=build and test Signed-… [View More]off-by: Ben Chuang <benchuanggli(a)gmail.com> Change-Id: Iacfa3c668a52d1bae15fe82f1c614d0ebd93a957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9755/gl9755.h 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index 6dfac47..a5778e3 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -28,6 +28,9 @@ reg |= CFG2_LAT_L1_64US; pci_write_config32(dev, CFG2, reg); + /* Turn off debug mode to enable SCP/OCP */ + pci_and_config32(dev, CFG3, ~SCP_DEBUG); + /* Set Vendor Config to be non-configurable */ pci_and_config32(dev, CFG, ~CFG_EN); } diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h index aa20a52..bc347fb 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.h +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -15,5 +15,7 @@ #define SNOOP_SCALE (0x3 << 10) #define NO_SNOOP_VALUE (0x25 << 16) #define NO_SNOOP_SCALE (0x3 << 26) +#define CFG3 0x70 +#define SCP_DEBUG (0x1 << 19) #endif /* DRIVERS_GENESYSLOGIC_GL9755_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacfa3c668a52d1bae15fe82f1c614d0ebd93a957 Gerrit-Change-Number: 51000 Gerrit-PatchSet: 4 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Greg Tu <greg.tu(a)genesyslogic.com.tw> Gerrit-CC: HsuanYang Chen <ynop77(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: 陳建宏 <renius.chen(a)genesyslogic.com.tw> Gerrit-MessageType: merged [View Less]

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Change in coreboot[master]: mb/intel/shadowmountain: Enable early EC Software Sync
by Patrick Georgi (Code Review) 05 May '21

05 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52416 ) Change subject: mb/intel/shadowmountain: Enable early EC Software Sync ...................................................................... mb/intel/shadowmountain: Enable early EC Software Sync BUG=None TEST=Build and boot to OS on shadowmountain. Ensure that the EC Software Sync is complete. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf … [View More]

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Change in coreboot[master]: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
by Michael Niewöhner (Code Review) 05 May '21

05 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52846 ) Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52846/comment/0ac6067d_031cb411 PS7, Line 143: uint8_t … [View More]

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coreboot-gerrit May 2021