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Change subject: mb/google/octopus: add audio codec into SSFC support for Phaser
......................................................................
mb/google/octopus: add audio codec into SSFC support for Phaser
Add audio codec module RT5682I in project.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
---
M src/mainboard/google/octopus/Kconfig.name
M src/mainboard/google/octopus/variants/phaser/gpio.c
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52878/6
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Change subject: mb/google/octopus: add audio codec into SSFC support for Phaser
......................................................................
Patch Set 5:
This change is ready for review.
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Change subject: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52873/comment/f4f09459_d08c548a
PS4, Line 7: soc/intel/{adl, tgl, jsl}: Don't disable bus master on PMC device in sleep smi
:
: We found system hang if the shutdown is triggered before fsps.
: This is due to the io decode enable on pmc is disabled by
: busmaster_disable_on_bus function.
: Hence, the slp_en on acpi pm1_cnt register doesn't succeed.
: So this change skip pmc bus disable before shutdown.
:
: The reason issue is not reproduced after fsps is beacause pmc pci
: device is hidden after fsps.
: That's why busmaster_disable_on_bus won't clear io deocde on pmc device.
> suggestion: […]
thanks for your suggestion.
i've changed the commit msg.
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Change subject: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/52874/comment/01d1b6f2_147d8a08
PS5, Line 101: /*
: * Now that all APs have been relocated as well as the BSP let SMIs
: * start flowing.
: */
> Can you please update all of these comments as to the reason why the `_no_powrbtn` variant is used h […]
done
File src/soc/intel/alderlake/pmc.c:
https://review.coreboot.org/c/coreboot/+/52874/comment/893b31d4_a96a3f77
PS5, Line 148: (FSPS)
> nit: space after `(`, also please spell it `FSP-S`
done
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Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
......................................................................
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently
enabled and before FSP-S exits, when the SMI handler disables
bus mastering for all devices, it inadvertently also disables
the PMC's I/O decoding, so the register write to actually go into
S5 does not succeed, and the system hangs.
This can be solved by skipping the PMC when disabling bus
mastering in the SMI handler, for which a callback,
smihandler_soc_disable_busmaster is provided.
BUG=b:186194102, b:186815114
Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
---
M src/soc/intel/alderlake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
3 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/52873/5
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Hello build bot (Jenkins), Furquan Shaikh, Kane Chen, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
......................................................................
soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.
This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.
BUG=b:186194102, b:186815114
Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/tigerlake/cpu.c
M src/soc/intel/tigerlake/pmc.c
6 files changed, 44 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/52874/6
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52908 )
Change subject: mb/google/guybrush: Configure wake resource for WiFi
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52908/comment/a32487d9_b86795dc
PS1, Line 13: is added to SSDT.
> I am trying to wake on WiFi. Unfortunately the device is not waking up. […]
Can you please try configuring the pad to `PAD_SCI` instead of `PAD_NF_SCI`. I had asked this question on https://review.coreboot.org/c/coreboot/+/51756/comment/21b7f1ba_4d7691e6/. But, it was conveniently ignored.
Reference from zork: b/162605108#comment6
If changing to PAD_SCI does not help, you can check a few things:
1. Is the mapping of GPIO_2 to GEVENT_8 looks correct in the OS?
2. Is the GPE_EN bit set when going into suspend? (probably will have to use S3 for this so that you can dump the state just before suspending).
3. Is GPE_STS bit set on resume?
4. Is the behavior same in case of S3 and S0i3?
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Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52847 )
Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device
......................................................................
drivers/i2c/generic: Set S0W to D3hot for wake device
If device is supported as a wake source, _S0W should be set to D3hot.
This ensures that the device is put into D3hot by the OSPM.
Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM.
The devices we are currently looking at for touchscreen/touchpad
do not really support auxiliary power and so do not support wake from D3cold.
BUG=b:186070097
TEST=build and check device wake state _S0W set to 3 in ssdt table.
Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
---
M Documentation/acpi/devicetree.md
M src/drivers/i2c/generic/generic.c
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md
index f121698..c184fa0 100644
--- a/Documentation/acpi/devicetree.md
+++ b/Documentation/acpi/devicetree.md
@@ -65,7 +65,7 @@
0x0000002D,
}
})
- Name (_S0W, 0x04) // _S0W: S0 Device Wake State
+ Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT) // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x15, // GPE #21
@@ -196,7 +196,7 @@
### _S0W (S0 Device Wake State)
_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is 4, representing _D3cold_.
+which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
### _PRW (Power Resources for Wake)
_PRW indicates the power resources and events required for wake. There are no
diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c
index 1c7267e..656b9e6 100644
--- a/src/drivers/i2c/generic/generic.c
+++ b/src/drivers/i2c/generic/generic.c
@@ -98,7 +98,7 @@
/* Wake capabilities */
if (config->wake) {
- acpigen_write_name_integer("_S0W", 4);
+ acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
acpigen_write_PRW(config->wake, 3);
}
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Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52725 )
Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup
......................................................................
Patch Set 10:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52725/comment/6ed814f0_4305951a
PS9, Line 11: Add fake touchscreen enable_pin GPP_D9 to ensure meet power sequence T11 in spec v0.8.
> How? What is spec v0. […]
Keep current setting, just add wake source.
Thanks
https://review.coreboot.org/c/coreboot/+/52725/comment/f2824771_57943ea6
PS9, Line 13: empty pin
> when you say "empty" do you mean NC or do you mean GND plane? I assume you mean NC but I wanted to c […]
Yes, GPP_D9 is NC ping on dooly board.
Thanks
Patchset:
PS10:
Please help review.
Thanks
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Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52902 )
Change subject: soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables
......................................................................
Patch Set 1: Code-Review+1
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