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Change subject: verstage: Add debug print when returning from verstage
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Patch Set 2: Code-Review+2
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Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51758 )
Change subject: QC SOCs: update code moved to common/
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Patch Set 7:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51758/comment/c71f4904_ed35cc62
PS5, Line 7: QC SOCs: update code moved to common/
> I will address
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/51758/comment/795d14a4_945b0219
PS7, Line 7: update code moved to common/
> That sounds strange. Maybe: […]
Ack
Patchset:
PS7:
> Looks good once you update the message
updated commit description with details
File src/soc/qualcomm/qcs405/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/51758/comment/6f4cb095_b6c71f54
PS7, Line 12: all-$(CONFIG_DRIVERS_UART) += uart.c
> I think that it's ok to include the Makefile cleanup code in this CL. […]
added detailed description in commit message
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Change subject: mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52110/comment/17aab61f_08b31cb8
PS1, Line 9: With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.
Sorry, I do not fully grasp the explanation. If it’s related to DDR4, why can’t FSP detect it’s FSP and set the correct setting itself?
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Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph.
Hello Varshit B Pandya, build bot (Jenkins), Dana Alkattan, Francois Toguo Fotso, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50138
to look at the new patch set (#24).
Change subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
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soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
Added new LPC and IGD device IDs for Alderlake M.
Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c
TEST=Check if platform information print is coming properly in coreboot
Change-Id: If33c43da8cbd786261b00742e342f0f01622c607
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/lpc/lpc.c
4 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/50138/24
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