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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52104 )
Change subject: soc/intel/alderlake: Drop unreferenced `InternalGfx`
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Patch Set 2:
(1 comment)
Patchset:
PS1:
> Uh, can you please point out the exact line you're referring to? Line 27 is ` PCH_PCIE_RP,` here.
oops, line 64
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Change subject: util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))
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Patch Set 1: Code-Review+2
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50654 )
Change subject: util/bincfg: Clean up Makefile
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Patch Set 3:
(1 comment)
File util/bincfg/Makefile:
https://review.coreboot.org/c/coreboot/+/50654/comment/3a8918d8_ca8fcbaf
PS1, Line 30: ./bincfg
> When the follow-up patch is ready, mind linking to it in a reply to this comment thread? Thanks!
https://review.coreboot.org/c/coreboot/+/52111
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Change subject: verstage: Add debug print when returning from verstage
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Patch Set 2: Code-Review+2
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Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51758 )
Change subject: QC SOCs: update code moved to common/
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Patch Set 7:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51758/comment/c71f4904_ed35cc62
PS5, Line 7: QC SOCs: update code moved to common/
> I will address
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/51758/comment/795d14a4_945b0219
PS7, Line 7: update code moved to common/
> That sounds strange. Maybe: […]
Ack
Patchset:
PS7:
> Looks good once you update the message
updated commit description with details
File src/soc/qualcomm/qcs405/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/51758/comment/6f4cb095_b6c71f54
PS7, Line 12: all-$(CONFIG_DRIVERS_UART) += uart.c
> I think that it's ok to include the Makefile cleanup code in this CL. […]
added detailed description in commit message
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52110 )
Change subject: mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52110/comment/17aab61f_08b31cb8
PS1, Line 9: With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.
Sorry, I do not fully grasp the explanation. If it’s related to DDR4, why can’t FSP detect it’s FSP and set the correct setting itself?
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