coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/mancomb: Enable early EC Software Sync
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Hello Raul Rangel, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52124 to look at the new patch set (#2). Change subject: mb/google/mancomb: Enable early EC Software Sync ...................................................................... mb/google/mancomb: Enable early EC Software Sync BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 --- M src/mainboard/google/mancomb/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/52124/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Gerrit-Change-Number: 52124 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
by Maulik V Vaghela (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Varshit B Pandya, Sridhar Siricilla, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50138 ) Change subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M ...................................................................... Patch Set 24: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50138/comment/8dce0edd_55ee1eaa PS23, Line 10: Also > nit […] Done https://review.coreboot.org/c/coreboot/+/50138/comment/a501f376_b10d3fae PS23, Line 12: BUG=None : BRANCH=None > don't need Done https://review.coreboot.org/c/coreboot/+/50138/comment/83e717af_dffab669 PS23, Line 14: c > nit: Check Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Gerrit-Change-Number: 50138 Gerrit-PatchSet: 24 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Dana Alkattan <dana.alkattan(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 05:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
by Maulik V Vaghela (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph. Hello Varshit B Pandya, build bot (Jenkins), Dana Alkattan, Francois Toguo Fotso, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50138 to look at the new patch set (#24). Change subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M ...................................................................... soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/lpc/lpc.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/50138/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/50138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Gerrit-Change-Number: 50138 Gerrit-PatchSet: 24 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Dana Alkattan <dana.alkattan(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Enable early EC Software Sync
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52124 ) Change subject: mb/google/mancomb: Enable early EC Software Sync ...................................................................... mb/google/mancomb: Enable early EC Software Sync BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 --- M src/mainboard/google/mancomb/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/52124/1 diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index ba8f1d4..6a9692c 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -26,6 +26,7 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_EARLY_EC_SYNC config FMDFILE string -- To view, visit https://review.coreboot.org/c/coreboot/+/52124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Gerrit-Change-Number: 52124 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Add eSPI GPIO back to init table
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52123 ) Change subject: mb/google/mancomb: Add eSPI GPIO back to init table ...................................................................... mb/google/mancomb: Add eSPI GPIO back to init table GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/52123/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 1eb1b80..29fa866 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -108,7 +108,14 @@ /* CLK_REQ0_L */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* GPIO_93 - GPIO_103: Not available */ - /* GPIO_104 - GPIO_108: eSPI configured in early stage */ + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* EGPIO109 */ PAD_NC(GPIO_109), /* GPIO_110 - GPIO_112: Not available */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Gerrit-Change-Number: 52123 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Configure UART0 gpio in early stage
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52122 ) Change subject: mb/google/mancomb: Configure UART0 gpio in early stage ...................................................................... mb/google/mancomb: Configure UART0 gpio in early stage BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/52122/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 5a6f2ac..1eb1b80 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -166,6 +166,10 @@ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), }; /* GPIO configuration for sleep */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Gerrit-Change-Number: 52122 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 ) Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52115/comment/7ce0ba4a_a57a3a5e PS1, Line 54: HIGH > They get toggled by the FSP. […] But why? In my opinion that is not the right direction to take. All the GPIOs must be configured correctly by coreboot before handing over to FSP/AGESA to initialize root ports. There are requirements w.r.t. timings which are best handled by coreboot rather than spreading the configuration across coreboot and FSP/AGESA. https://review.coreboot.org/c/coreboot/+/52115/comment/eb81ba8d_81d4d31c PS1, Line 169: /* EN_PP3300_WLAN */ > I'm sure there are, but we haven't looked at that yet. […] Why is this dependent on PSP verstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 04:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 ) Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52115/comment/cda35922_3bda6ab5 PS1, Line 54: HIGH > Don't you need the *_RST{_L} signals to be deasserted before FSP-M runs? They get toggled by the FSP. https://review.coreboot.org/c/coreboot/+/52114 https://review.coreboot.org/c/coreboot/+/52115/comment/5c29360e_9222ed60 PS1, Line 169: /* EN_PP3300_WLAN */ > Is there any timing requirement between EN_PP3300_WLAN and WLAN_DISABLE signals? Same for WWAN? I'm sure there are, but we haven't looked at that yet. We're going to have to adjust the timings once we start running the early gpio init in PSP verstage. Tracked in b/184598323 - guybrush: Look at PCIe power-on timings and make sure that they're being met. -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 04:25:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable USB ports in devicetree
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Raul Rangel, Martin Roth, Mathew King, EricR Lai. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52119 ) Change subject: mb/google/mancomb: Enable USB ports in devicetree ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: No idea to add USB HUB... -- To view, visit https://review.coreboot.org/c/coreboot/+/52119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Gerrit-Change-Number: 52119 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 04:24:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable USB ports in devicetree
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52119 ) Change subject: mb/google/mancomb: Enable USB ports in devicetree ...................................................................... mb/google/mancomb: Enable USB ports in devicetree BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/52119/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 305ba0b..b368574 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -46,6 +46,72 @@ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""Rear Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Rear Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""Front Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB HUB"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB HUB"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)" + device ref usb2_port6 on end + end + end + end + end end device ref lpc_bridge on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/52119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Gerrit-Change-Number: 52119 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021