coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: mb/prodrive/hermes: Properly pack EEPROM structures
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51980 ) Change subject: mb/prodrive/hermes: Properly pack EEPROM structures ...................................................................... mb/prodrive/hermes: Properly pack EEPROM structures To pack a struct, the `__packed` attribute must come after the `struct` keyword. Moreover, unions cannot be packed (structs inside unions can, though). Correct uses of `__packed` so that EEPROM structs get packed. Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: <wouter.eckhardt(a)prodrive-technologies.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 1 file changed, 17 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved wouter.eckhardt(a)prodrive-technologies.com: Looks good to me, but someone else must approve diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index e6e5f39..58ecb08 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -2,8 +2,8 @@ #include <soc/ramstage.h> -__packed union eeprom_dimm_layout { - struct { +union eeprom_dimm_layout { + struct __packed { char name[50]; char manufacturer[50]; uint8_t ranks; @@ -16,10 +16,13 @@ uint8_t raw[0x80]; }; -__packed struct eeprom_board_layout { +_Static_assert(sizeof(union eeprom_dimm_layout) == 0x80, + "union eeprom_dimm_layout has invalid size!"); + +struct __packed eeprom_board_layout { uint32_t signature; union { - struct { + struct __packed { char cpu_name[50]; uint8_t cpu_count; uint32_t cpu_max_non_turbo_frequency; @@ -30,10 +33,13 @@ }; }; -__packed struct eeprom_board_settings { +_Static_assert(sizeof(struct eeprom_board_layout) == (617 + sizeof(uint32_t)), + "struct eeprom_board_layout has invalid size!"); + +struct __packed eeprom_board_settings { uint32_t signature; union { - struct { + struct __packed { uint8_t secureboot; uint8_t primary_video; uint8_t deep_sx_enabled; @@ -48,13 +54,16 @@ }; }; -__packed struct eeprom_bmc_settings { +_Static_assert(sizeof(struct eeprom_board_settings) == (9 + sizeof(uint32_t)), + "struct eeprom_board_settings has invalid size!"); + +struct __packed eeprom_bmc_settings { uint8_t pcie_mux; uint8_t hsi; }; /* The EEPROM on address 0x57 has the following vendor defined layout: */ -__packed struct eeprom_layout { +struct __packed eeprom_layout { union { uint8_t RawFSPMUPD[0x600]; FSPM_UPD mupd; -- To view, visit https://review.coreboot.org/c/coreboot/+/51980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3 Gerrit-Change-Number: 51980 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Matt DeVillier, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: Nico, any objection to getting this in as it is now? -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 14 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 06:49:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52100 ) Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52100/comment/e6860d04_9029157a PS1, Line 13: . > Done. I've specified that I only updated platforms with the InternalGfx UPD. alderlake is missing ;) see CB:52104 -- To view, visit https://review.coreboot.org/c/coreboot/+/52100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Gerrit-Change-Number: 52100 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 06:47:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Docs/mb/lenovo/t420: List working, tested and non-working features
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51952 ) Change subject: Docs/mb/lenovo/t420: List working, tested and non-working features ...................................................................... Docs/mb/lenovo/t420: List working, tested and non-working features Signed-off-by: Piotr Szymaniak <szarpaj(a)grubelek.pl> Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/lenovo/t420.md 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 00ce45f..189649b 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -18,6 +18,40 @@ Steps to access the flash IC are described here [T4xx series]. +## Working + * CPU: Sandy Bridge i5-2520M, i7-2670QM + * RAM module combinations of 2G+0, 2G+2G, 4G+0 + * mSATA + * USB + * Video (Intel integrated) + * Sound (integrated speakers, integrated mic, external headphones, external mic) + * LAN + * Mini-PCIe slots (WLAN) + * Bluetooth + * Linux + * Windows 10 (through SeaBIOS as payload, using a VGA BIOS) + * DVD-ROM drive + * SD card slot + * TrackPoint + * Touchpad + * Webcam + * Fn hotkeys (backlight control, thinklight) + * Thinklight + * Mute button (Speaker only) + * Mini Jack audio (headphones) + * Suspend (Linux) + +## Not tested + * DSub (VGA) out + * DisplayPort out + * eSATA + * ExpressCard + * WWAN + +## Not working/TODOs + * Mutemic button doesn't mute + * Suspend (Windows 10) + [T4xx series]: t4xx_series.md [flashing tutorial]: ../../flash_tutorial/ext_power.md [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md -- To view, visit https://review.coreboot.org/c/coreboot/+/51952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1 Gerrit-Change-Number: 51952 Gerrit-PatchSet: 7 Gerrit-Owner: szarpaj(a)grubelek.pl Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/lenovo/t420: Copy HDA verbs from vendor firmware
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51612 ) Change subject: mb/lenovo/t420: Copy HDA verbs from vendor firmware ...................................................................... mb/lenovo/t420: Copy HDA verbs from vendor firmware Background story (I think that's what great in opensource - ppl leave there part of their lives): ;-) While trying to fix audio jack not working with coreboot and Windows 10 with some help from hell__ and nico_h on IRC nico_h discovered that t420 and t430 hda_verb.c are the same: <nico_h> oddly, in coreboot source T420 and T430 have the same numbers for very different codecs... I suspect copy-pasta Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config in vendor BIOS helped with the updated config. Connecting audio jack now works flawless both in Linux and Windows. Audio-related keyboard buttons: volup, voldown, mute works fine both in Linux (Debian-based) and Windows 10. mutemic button works (tested ie. with xev) but both in Linux and Windows 10 wont light up or makes any effect. +-----------------------------------+ | init_pin_config dump from: | +----= VENDOR =---+---= coreboot =--+ | 0x19 0x04211040 | 0x19 0x04211040 | | 0x1a 0x61a19050 | 0x1a 0x61a19050 | | 0x1b 0x04a11060 | 0x1b 0x04a11060 | | 0x1c 0x6121401f | 0x1c 0x6121401f | | 0x1d 0x40f001f0 | 0x1d 0x40f001f0 | | 0x1e 0x40f001f0 | 0x1e 0x40f001f0 | | 0x1f 0x90170110 | 0x1f 0x90170110 | | 0x20 0x40f001f0 | 0x20 0x40f001f0 | | 0x22 0x40f001f0 | 0x22 0x40f001f0 | | 0x23 0x90a60170 | 0x23 0x90a60170 | +-----------------+-----------------+ Tested-by: Piotr Szymaniak Signed-off-by: Piotr Szymaniak <szarpaj(a)grubelek.pl> Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t420/hda_verb.c 1 file changed, 20 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 6f27490..3d5deef 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -11,17 +11,17 @@ 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ 0x17aa21ce, /* Subsystem ID */ 13, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21d2), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_SUBVENDOR(0, 0x17aa21ce), + AZALIA_PIN_CFG(0, 0x19, 0x04211040), + AZALIA_PIN_CFG(0, 0x1a, 0x61a19050), + AZALIA_PIN_CFG(0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0, 0x1c, 0x6121401f), + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a60170), /* Misc entries */ 0x00b707C0, /* Enable PortB as Output with HP amp */ @@ -35,6 +35,15 @@ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ + + /* --- Codec #3 --- */ + 0x80862805, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), }; const u32 pc_beep_verbs[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/51612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410 Gerrit-Change-Number: 51612 Gerrit-PatchSet: 7 Gerrit-Owner: szarpaj(a)grubelek.pl Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/intel/fsp1_1: Drop dead MMA code
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51951 ) Change subject: drivers/intel/fsp1_1: Drop dead MMA code ...................................................................... drivers/intel/fsp1_1: Drop dead MMA code The only FSP 1.1 platform with MMA support is Skylake. As it now uses Kaby Lake FSP 2.0, this code is no longer useful. Drop it. Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/drivers/intel/fsp1_1/Makefile.inc D src/drivers/intel/fsp1_1/mma_core.c 2 files changed, 0 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4259237..4b8e0a8 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -16,14 +16,12 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c -ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c deleted file mode 100644 index 6e50373..0000000 --- a/src/drivers/intel/fsp1_1/mma_core.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <fsp/util.h> -#include <fsp/romstage.h> -#include <fsp/soc_binding.h> - -#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ - { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } - -int fsp_locate_mma_results(const void **mma_hob, size_t *mma_hob_size) -{ - const void *mma_hob_start; - const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; - - mma_hob_start = get_first_guid_hob(&mma_results_guid); - if (!mma_hob_start) - return -1; - *mma_hob = GET_GUID_HOB_DATA(mma_hob_start); - *mma_hob_size = GET_HOB_LENGTH(mma_hob); - - if (!(*mma_hob_size) || !(*mma_hob)) - return -1; - return 0; -} - -void setup_mma(MEMORY_INIT_UPD *memory_cfg) -{ - struct mma_config_param mma_cfg; - - if (mma_locate_param(&mma_cfg)) { - printk(BIOS_DEBUG, "MMA: set up failed\n"); - return; - } - - soc_update_memory_params_for_mma(memory_cfg, &mma_cfg); - printk(BIOS_DEBUG, "MMA: set up completed successfully\n"); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/51951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd Gerrit-Change-Number: 51951 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: York Yang <york.yk.yang(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/zork: update DRAM table for morphius
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51947 ) Change subject: mb/google/zork: update DRAM table for morphius ...................................................................... mb/google/zork: update DRAM table for morphius Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb index was generated by gen_part_id BUG=b:184024142 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt M src/mainboard/google/zork/variants/morphius/spd/Makefile.inc M src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt 4 files changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 21565c6..e32bd30 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -14,3 +14,5 @@ K4AAG165WA-BCTD,ddr4-spd-8.hex H5ANAG6NDMR-XNC,ddr4-spd-2.hex H5ANAG6NCJR-XNC,ddr4-spd-9.hex +K4AAG165WB-BCWE,ddr4-spd-9.hex +MT40A1G16RC-062E:B,ddr4-spd-9.hex diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 805ede4..0851ab2 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC, MT40A1G16RC-062E:B SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E diff --git a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt index b061000..399228e 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ H5ANAG6NCMR-XNC 8 (1000) K4A8G165WC-BCWE 9 (1001) H5ANAG6NCJR-XNC 0 (0000) +MT40A1G16RC-062E:B 0 (0000) diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt index 87bbb36..6e99e76 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -16,3 +16,4 @@ H5ANAG6NCMR-XNC, 8 K4A8G165WC-BCWE, 9 H5ANAG6NCJR-XNC +MT40A1G16RC-062E:B -- To view, visit https://review.coreboot.org/c/coreboot/+/51947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f Gerrit-Change-Number: 51947 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD
by Kevin Chiu (Code Review) 06 Apr '21

06 Apr '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44861 ) Change subject: mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD ...................................................................... mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD BUG=b:165956925 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- A src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44861/1 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex new file mode 100644 index 0000000..8483e99 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 52 43 2D 30 36 32 45 3A 42 20 20 31 80 2C +42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/44861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Gerrit-Change-Number: 44861 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: soc/intel/skylake: Always use `CHIPSET_LOCKDOWN_COREBOOT`
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52096 ) Change subject: soc/intel/skylake: Always use `CHIPSET_LOCKDOWN_COREBOOT` ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I agree this isn't elegant. However, FSP lockdown is tied into soc/intel/common, so it's not like I can drop it in one patch. Agreed. We first would need to convert all boards. However, I suspect not everyone will agree here. > This change is a stopgap to prevent new boards from accidentally using CHIPSET_LOCKDOWN_FSP by omission. What about adding a checkpatch script for that? > Another approach would be to invert the enum values for chipset lockdown to make CHIPSET_LOCKDOWN_COREBOOT the default value, but that also requires checking each and every board. I'll see what I can do. I never understood why that is board-specific anyway. Convert that to Kconfig and make cb lockdown the default? That way people who <3 FSP can keep it if they want to... -- To view, visit https://review.coreboot.org/c/coreboot/+/52096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a1a2fab166aa3bfe8e0b07f155f57f2bf745e3 Gerrit-Change-Number: 52096 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 06:45:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Drop unreferenced `InternalGfx`
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52104 ) Change subject: soc/intel/alderlake: Drop unreferenced `InternalGfx` ...................................................................... Patch Set 2: -Code-Review (1 comment) Patchset: PS1: > oops, line 64 Sorry, I still don't get what you mean. This is the UPD field: dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) m_cfg->InternalGfx = 1; else m_cfg->InternalGfx = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/52104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Gerrit-Change-Number: 52104 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 06:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021