coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/mancomb: Enable PCIe devices in devicetree
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52118 ) Change subject: mb/google/mancomb: Enable PCIe devices in devicetree ...................................................................... mb/google/mancomb: Enable PCIe devices in devicetree BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/52118/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index c4ef3f5..305ba0b 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -39,6 +39,11 @@ }" device domain 0 on + device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_1 on end # SD + device ref gpp_bridge_2 on end # LAN + device ref gpp_bridge_3 on end # NVMe + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) end -- To view, visit https://review.coreboot.org/c/coreboot/+/52118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Gerrit-Change-Number: 52118 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Add initial fch irq routing
by EricR Lai (Code Review) 06 Apr '21

06 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52117 ) Change subject: mb/google/mancomb: Add initial fch irq routing ...................................................................... mb/google/mancomb: Add initial fch irq routing BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef --- M src/mainboard/google/mancomb/mainboard.c 1 file changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52117/1 diff --git a/src/mainboard/google/mancomb/mainboard.c b/src/mainboard/google/mancomb/mainboard.c index 2205f8f..ebf9d4d 100644 --- a/src/mainboard/google/mancomb/mainboard.c +++ b/src/mainboard/google/mancomb/mainboard.c @@ -1,10 +1,85 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/amd_pci_util.h> #include <baseboard/variants.h> #include <device/device.h> +#include <soc/acpi.h> #include <variant/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} guybrush_fch[] = { + { PIRQ_A, PIRQ_NC, PIRQ_NC }, + { PIRQ_B, PIRQ_NC, PIRQ_NC }, + { PIRQ_C, PIRQ_NC, PIRQ_NC }, + { PIRQ_D, PIRQ_NC, PIRQ_NC }, + { PIRQ_E, PIRQ_NC, PIRQ_NC }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, PIRQ_NC }, + { PIRQ_H, PIRQ_NC, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(guybrush_fch); i++) { + entry = guybrush_fch + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + static void mainboard_configure_gpios(void) { size_t base_num_gpios, override_num_gpios; @@ -25,6 +100,10 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + + init_tables(); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Gerrit-Change-Number: 52117 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTE
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51935 ) Change subject: mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTE ...................................................................... mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTE Loading wifi_sar-vilboz-2.hex for vilboz LTE sku. Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku. BUG=b:183902165, b:176211194, b:183913210 BRANCH=firmware-zork-13434.B TEST=Build coreboot and load the wifi sar table by fw_config Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 3 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 5006b92..43ca0e5 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -64,7 +64,6 @@ | |Vilboz|Vilboz14|Vilboz14|Vilboz|NA|Vilboz360|NA|Vilboz360| | |WiFi |WiFi |LTE |LTE | |WiFi | |LTE | +----------+------+--------+--------+------+--+---------+--+---------+ -|SAR[26] |0 |0 |0 |0 |0 |0 |0 |0 | |SAR[25] |0 |0 |0 |0 |1 |1 |1 |1 | |SAR[24] |0 |0 |1 |1 |0 |0 |1 |1 | |SAR[23] |0 |1 |0 |1 |0 |1 |0 |1 | @@ -83,14 +82,11 @@ case 1: return "wifi_sar-vilboz-0.hex"; case 3: - /* - TODO: Set default first. It will be replaced after the - new table is generated. - */ - return WIFI_SAR_CBFS_DEFAULT_FILENAME; + return "wifi_sar-vilboz-2.hex"; case 5: - case 7: return "wifi_sar-vilboz-1.hex"; + case 7: + return "wifi_sar-vilboz-3.hex"; default: return WIFI_SAR_CBFS_DEFAULT_FILENAME; } -- To view, visit https://review.coreboot.org/c/coreboot/+/51935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222 Gerrit-Change-Number: 51935 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 ) Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52115/comment/04b4b8ca_d117d19e PS1, Line 54: HIGH Don't you need the *_RST{_L} signals to be deasserted before FSP-M runs? https://review.coreboot.org/c/coreboot/+/52115/comment/a7a452a6_b2866612 PS1, Line 169: /* EN_PP3300_WLAN */ Is there any timing requirement between EN_PP3300_WLAN and WLAN_DISABLE signals? Same for WWAN? -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 03:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
by Julius Werner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Martin Roth, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51838 ) Change subject: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test ...................................................................... Patch Set 2: (7 comments) Patchset: PS2: > Hi, hmmm, thought I'd give it a quick look and then... all the […] Yeah, unfortunately I haven't got any attention at all on LKML yet. Maybe it would help if you post these there, create a bit more back-and-forth on the patch series to bump it to the top of the maintainer's inbox. File util/lint/checkpatch.pl: https://review.coreboot.org/c/coreboot/+/51838/comment/67fa9966_cb625ad9 PS2, Line 1345: @stack = (['', 0]) if ($#stack == -1); > Looks like this wouldn't be needed anymore? With the new index checks, […] Right, I guess I could drop it. https://review.coreboot.org/c/coreboot/+/51838/comment/d16b0ec5_c19f7ed6 PS2, Line 1553: $level = $stack[$#stack - 1]; > Looks like this suffers the same? Yeah, looks like it. I haven't actually looked into what this set of functions does and where it is used. But in isolation this looks like the same bug. https://review.coreboot.org/c/coreboot/+/51838/comment/9a595e55_cf2364b1 PS2, Line 3629: s > The `s` modifier looks suspicious. AIUI, it means the `.` could match […] Probably, yeah. This is from Ivo's original patch which I didn't want to modify upstream for attribution reasons. Maybe he thought that without the /s he couldn't match "\n" at all (some regex engines work that way, although I think Perl's doesn't... at least the thing for labels I wrote below seemed to work without it). If you think it's important enough I can put another cleanup patch behind Ivo's to fix up minor stuff. https://review.coreboot.org/c/coreboot/+/51838/comment/a397bca7_a39e6180 PS2, Line 3638: \s* > Is there a point to match preceding whitespace if we don't match from the start? No idea, this is also Ivo's stuff. Probably not. https://review.coreboot.org/c/coreboot/+/51838/comment/0b0befbd_2a32ab6c PS2, Line 3642: \s*? > I couldn't find any example where this matches. […] I think ctx_statement_block() just doesn't handle do-while perfectly, and this is meant to work around that. When parsing a do-while statement, $stat ends up counting the `do { ... }` up until the closing brace and then $s_next gets the ` while (...)`, starting with the leading space which makes it look indented. This will eat the while part so that s_next really captures the next statement. (That's why it's using `^` instead of `\n`, too, because it's really only about the start of the whole statement.) https://review.coreboot.org/c/coreboot/+/51838/comment/3972f73b_a15404dc PS2, Line 3663: stat_real > Nit, somehow $stat_real is missing the closing brace (if it was a block with braces). Hmm... yeah, not sure, $stat_real already falls out of the existing code above. This is printing it the same way the existing warning is printing it, I hope that's good enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/51838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f Gerrit-Change-Number: 51838 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 03:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49317 ) Change subject: drivers/uart: Add ACPI SPCR table generation ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/zork: Select DRIVERS_WIFI_GENERIC option
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50146 ) Change subject: mb/google/zork: Select DRIVERS_WIFI_GENERIC option ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23ee53568f1ace95597c9a7d4f46af73d309b8d7 Gerrit-Change-Number: 50146 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/zork: Add timestamps around forced delay
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47313 ) Change subject: mb/google/zork: Add timestamps around forced delay ...................................................................... mb/google/zork: Add timestamps around forced delay Due to a hardware design change, early boards need an additional delay when initializing the fingerprint sensor. Add a timestamp around the delay so it can be subtracted from the timestamp calculation if desired. BUG=b:171837716 TEST=Look at new timestamp data BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I801f0af6ef54f92865fd627dee12bb023cef534f --- M src/mainboard/google/zork/variants/berknip/gpio.c M src/mainboard/google/zork/variants/morphius/gpio.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47313/1 diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index a4d5a64..b91078e 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -7,6 +7,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> +#include <timestamp.h> static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = { /* PEN_DETECT_ODL - no used */ @@ -64,7 +65,9 @@ /* Berknip board versions prior to v4 need an extra delay here */ if (board_version <= 3) { + timestamp_add_now(TS_DELAY_START); mdelay(550); + timestamp_add_now(TS_DELAY_END); } /* * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 14211b2..4f2781c 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -7,6 +7,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> +#include <timestamp.h> static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = { /* DMIC_SEL */ @@ -99,7 +100,9 @@ /* Morphius board versions prior to v5 need an extra delay here */ if (board_version <= 4) { + timestamp_add_now(TS_DELAY_START); mdelay(550); + timestamp_add_now(TS_DELAY_END); } /* * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out -- To view, visit https://review.coreboot.org/c/coreboot/+/47313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I801f0af6ef54f92865fd627dee12bb023cef534f Gerrit-Change-Number: 47313 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Disable USB_OC0_L on transition to S3
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48650 ) Change subject: mb/google/zork: Disable USB_OC0_L on transition to S3 ...................................................................... mb/google/zork: Disable USB_OC0_L on transition to S3 One of the second source USB charging port chips is erroneous triggering the overcurrent pin when we go into S3. Because this is used mainly to report the overcurrent situation to the OS and there is additional overcurrent protection, we can disable the function when the system goes into S3. It will get switched back to the overcurrent function when the system resumes. BUG=b:175646274 TEST=Build. Still needs to be functionally tested BRANCH=Zork Change-Id: I9d280c793a7989ebaa2fcc28531fe14e2adbfaef --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48650/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad517..234cd7d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -336,6 +336,9 @@ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_GPI(GPIO_16, PULL_NONE), + }; static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { @@ -348,6 +351,9 @@ PAD_GPO(GPIO_11, LOW), /* EN_PWR_FP */ PAD_GPO(GPIO_32, LOW), + + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_GPI(GPIO_16, PULL_NONE), }; const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) -- To view, visit https://review.coreboot.org/c/coreboot/+/48650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d280c793a7989ebaa2fcc28531fe14e2adbfaef Gerrit-Change-Number: 48650 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/50285 ) Change subject: mb/google/zork: Use Kconfig SPI speed & read mode in devicetree ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/50285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I116adf4fe0de5a2790894618ccff8ebf629fab34 Gerrit-Change-Number: 50285 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit April 2021