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Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51841 )
Change subject: mb/google/dedede/var/cret: Add audio support
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
LGTM, waiting Karthik to review. Thanks!
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Change subject: lint: checkpatch: Ignore ASSIGN_IN_IF and UNNECESSARY_ELSE errors
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51551/comment/dffc05af_4014ea96
PS3, Line 50: programmer
> 'programmers' because of the following 'their code' on the next line?
"their" is the appropriate pronoun for an unspecified singular individual in English (because you don't know whether to use "his" or "her"). See https://en.wikipedia.org/wiki/Singular_they
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Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52008
to look at the new patch set (#2).
Change subject: soc/amd/cezanne: Add support to perform early EC sync
......................................................................
soc/amd/cezanne: Add support to perform early EC sync
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52008/2
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Gerrit-MessageType: newpatchset
Karthik Ramasubramanian has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/52009 )
Change subject: mb/google/guybrush: Enable early EC Software Sync
......................................................................
mb/google/guybrush: Enable early EC Software Sync
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync
is complete.
Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/52009/2
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52008 )
Change subject: soc/amd/cezanne: Add support to perform early EC sync
......................................................................
soc/amd/cezanne: Add support to perform early EC sync
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also help
cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52008/1
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 643b067..57c1961 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -8,12 +8,16 @@
#include <console/console.h>
#include <fsp/api.h>
#include <program_loading.h>
+#include <security/vboot/vboot_common.h>
asmlinkage void car_stage_entry(void)
{
post_code(0x40);
console_init();
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec();
+
post_code(0x41);
fsp_memory_init(acpi_is_wakeup_s3());
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