coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51918 ) Change subject: mb/google/kukui: katsu: update the EDID and initial code ...................................................................... mb/google/kukui: katsu: update the EDID and initial code The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c index baf3dac..18e3cb7 100644 --- a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c +++ b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c @@ -9,7 +9,7 @@ .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 150451, + .pixel_clock = 165731, .lvds_dual_channel = 0, .refresh = 60, .ha = 1200, .hbl = 210, .hso = 100, .hspw = 10, @@ -20,7 +20,7 @@ }, .orientation = LB_FB_ORIENTATION_LEFT_UP, .init = { - INIT_DCS_CMD(0xB0, 0x41), + INIT_DCS_CMD(0xB0, 0x01), INIT_DCS_CMD(0xC3, 0x4F), INIT_DCS_CMD(0xC4, 0x40), INIT_DCS_CMD(0xC5, 0x40), @@ -63,13 +63,14 @@ INIT_DCS_CMD(0xD3, 0x04), INIT_DCS_CMD(0xD4, 0x01), INIT_DCS_CMD(0xD5, 0x00), - INIT_DCS_CMD(0xC6, 0x03), + INIT_DCS_CMD(0xD6, 0x03), INIT_DCS_CMD(0xD7, 0x04), INIT_DCS_CMD(0xD9, 0x01), INIT_DCS_CMD(0xDB, 0x01), INIT_DCS_CMD(0xE4, 0xF0), INIT_DCS_CMD(0xE5, 0x0A), INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xCC, 0x08), INIT_DCS_CMD(0xC2, 0x08), INIT_DCS_CMD(0xC4, 0x10), INIT_DCS_CMD(0xB0, 0x02), -- To view, visit https://review.coreboot.org/c/coreboot/+/51918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Gerrit-Change-Number: 51918 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... device/i2c_bus.c: Correct code style device: Correct code style Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition. - Remove unnecessary newlines. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50190 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/device/i2c_bus.c 1 file changed, 4 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Wim Vervoorn: Looks good to me, approved diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 93ec854..597a530 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -25,10 +25,8 @@ link = NULL; } - if (!link) { - printk(BIOS_ALERT, "%s Cannot find I2C or SMBus bus operations", - dev_path(dev)); - } + if (!link) + printk(BIOS_ALERT, "%s Cannot find I2C or SMBus bus operations", dev_path(dev)); return link; } @@ -79,8 +77,7 @@ return busdev->ops->ops_smbus_bus->send_byte(dev, val); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", - dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte", dev_path(busdev)); return -1; } @@ -140,8 +137,7 @@ return busdev->ops->ops_smbus_bus->write_byte(dev, off, val); } - printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", - dev_path(busdev)); + printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte", dev_path(busdev)); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packed
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51545 ) Change subject: vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packed ...................................................................... vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packed It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP but won't be fixed for CPX. This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Signed-off-by: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 1 file changed, 12 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 3c6f9a7..f36b568 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -56,6 +56,18 @@ #define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2) +// RC version number structure. +typedef struct { + uint8_t Major; + uint8_t Minor; + uint8_t Revision; + uint16_t BuildNumber; +} RC_VERSION; +// Note: the struct is not packed for a reason: it is not packed in FSP code. +// It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP +// but won't be fixed for CPX. +_Static_assert(sizeof(RC_VERSION) == 6, "Incorrect size of struct 'RC_VERSION'"); + #pragma pack(1) //--------------------------------------------------------------------------------------// @@ -77,16 +89,6 @@ TYPE_MAX_MMIO_BAR } MMIO_BARS; -/// -/// RC version number structure. -/// -typedef struct { - uint8_t Major; - uint8_t Minor; - uint8_t Revision; - uint16_t BuildNumber; -} RC_VERSION; - /** IIO PCIe Ports **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/51545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Gerrit-Change-Number: 51545 Gerrit-PatchSet: 5 Gerrit-Owner: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52021 ) Change subject: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT ...................................................................... vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. BUG = N/A TEST = run `make menuconfig` and boot Facebook FBG1701 Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52021 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/vendorcode/eltan/security/mboot/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Wim Vervoorn: Looks good to me, approved diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 540b7b2..4e30cf5 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -4,6 +4,7 @@ config VENDORCODE_ELTAN_MBOOT bool "Measure firmware with mboot." + depends on !VBOOT default n select VBOOT_LIB help -- To view, visit https://review.coreboot.org/c/coreboot/+/52021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Gerrit-Change-Number: 52021 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/facebook/monolith: Remove disabled devices from devicetree
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52018 ) Change subject: mb/facebook/monolith: Remove disabled devices from devicetree ...................................................................... mb/facebook/monolith: Remove disabled devices from devicetree All known on-chip PCI devices are disabled in the chipset devicetree. So they are removed from the mainboard devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52018 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/monolith/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 974d00e..13b3abc 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -225,12 +225,10 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # Thermal Subsystem - device pci 05.0 off end # SA IMGU device pci 08.0 on end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 -- To view, visit https://review.coreboot.org/c/coreboot/+/52018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1 Gerrit-Change-Number: 52018 Gerrit-PatchSet: 2 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTION
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52026 ) Change subject: mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTION ...................................................................... mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTION The romstage does not fit in RO_SECTION. Increase the CBFS size in RO_SECTION. BUG = N/A TEST = Boot Facebook FBG1701 with VBOOT enabled. Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/facebook/fbg1701/vboot-rw.fmd 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Wim Vervoorn: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd index 51ee470..ae7312c 100644 --- a/src/mainboard/facebook/fbg1701/vboot-rw.fmd +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -3,18 +3,18 @@ MISC_RW@0x0 0x08000 { RW_MRC_CACHE@0 0x08000 } - RW_SECTION_A@0x08000 0x578000 { + RW_SECTION_A@0x08000 0x568000 { VBLOCK_A@0x0 0x10000 RW_FWID_A@0x10000 0x40 - FW_MAIN_A(CBFS)@0x10040 0x567FC0 + FW_MAIN_A(CBFS)@0x10040 0x557FC0 } - WP_RO@0x580000 0x080000 { - RO_SECTION@0x0000 0x80000 { + WP_RO@0x570000 0x090000 { + RO_SECTION@0x0000 0x90000 { FMAP@0x0 0x400 RO_FRID@0xA00 0x40 RO_FRID_PAD@0xA40 0x5c0 GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x07B000 + COREBOOT(CBFS)@0x5000 0x08B000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/52026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e Gerrit-Change-Number: 52026 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/rules.h: Add ENV_TEST definition
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51803 ) Change subject: include/rules.h: Add ENV_TEST definition ...................................................................... include/rules.h: Add ENV_TEST definition Some functions/macros like assert() require redefinition for testing purposes. ENV_TEST is introduced to make it possible without using bypass hacks. This patch also adds a global __TEST__ define to TEST_CFLAGS for all test targets in order to enable ENV_TEST. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/rules.h M tests/Makefile.inc 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Paul Fagerburg: Looks good to me, approved diff --git a/src/include/rules.h b/src/include/rules.h index 6ebb37e..ec3d22d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -3,6 +3,12 @@ #ifndef _RULES_H #define _RULES_H +#if defined(__TEST__) +#define ENV_TEST 1 +#else +#define ENV_TEST 0 +#endif + #if defined(__TIMELESS__) #define ENV_TIMELESS 1 #else diff --git a/tests/Makefile.inc b/tests/Makefile.inc index ca974a9..027091c 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -39,6 +39,8 @@ TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -D__TEST__ + # Checkout Cmocka repository forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka) -- To view, visit https://review.coreboot.org/c/coreboot/+/51803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8 Gerrit-Change-Number: 51803 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: Add lib/uuid-test test case
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51976 ) Change subject: tests: Add lib/uuid-test test case ...................................................................... tests: Add lib/uuid-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I7f8498ad3d9d0d68b34aa0b48daca60545ec3f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51976 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/Makefile.inc A tests/lib/uuid-test.c 2 files changed, 99 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 613f8e5..cba4361 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -23,6 +23,7 @@ tests-y += crc_byte-test tests-y += compute_ip_checksum-test tests-y += memrange-test +tests-y += uuid-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -112,3 +113,6 @@ memrange-test-srcs += tests/stubs/console.c memrange-test-srcs += src/device/device_util.c +uuid-test-srcs += tests/lib/uuid-test.c +uuid-test-srcs += src/lib/hexstrtobin.c +uuid-test-srcs += src/lib/uuid.c diff --git a/tests/lib/uuid-test.c b/tests/lib/uuid-test.c new file mode 100644 index 0000000..c6e40f5 --- /dev/null +++ b/tests/lib/uuid-test.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <uuid.h> + +/* This test checks if parse_uuid() correctly parses UUID strings with correct format. + lib/uuid does not check UUID version nor variant. + If that changes tests should be updated as appropriate. */ +static void test_parse_uuid_correct(void **state) +{ + /* lib/uuid does not check UUID version nor variant. + If that changes tests should be updated as appropriate. */ + uint8_t uuid_buf[UUID_LEN] = { 0 }; + const char *uuid_correct = "00112233-4455-6677-8899-aabbccddeeff"; + const uint8_t uuid_correct_bin[UUID_LEN] = { + 0x33, 0x22, 0x11, 0x00, 0x55, 0x44, 0x77, 0x66, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, + }; + const char *uuid_zereos = "00000000-0000-0000-0000-000000000000"; + const uint8_t uuid_zeros_bin[UUID_LEN] = { 0 }; + const char *uuid_ff = "ffffffff-ffff-ffff-ffff-ffffffffffff"; + const uint8_t uuid_ff_bin[UUID_LEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + }; + + assert_int_equal(0, parse_uuid(uuid_buf, uuid_correct)); + assert_memory_equal(uuid_correct_bin, uuid_buf, UUID_LEN); + + assert_int_equal(0, parse_uuid(uuid_buf, uuid_zereos)); + assert_memory_equal(uuid_zeros_bin, uuid_buf, UUID_LEN); + + assert_int_equal(0, parse_uuid(uuid_buf, uuid_ff)); + assert_memory_equal(uuid_ff_bin, uuid_buf, UUID_LEN); +} + +/* This test validates parse_uuid() feeding it with incorrectly-formatted UUID strings. + No version/variant tests are performed due to lack of handling these properties + by lib/uuid. If that changes tests should be updated as appropriate.*/ +static void test_parse_uuid_incorrect(void **state) +{ + uint8_t uuid_buf[UUID_LEN] = { 0 }; + /* First separator at incorrect index */ + const char *uuid_incorrect_1 = "ab372d0-34cc1-1337-688b-2211337777ee"; + /* Incorrect characters */ + const char *uuid_incorrect_2 = "abbce711-5@51-7777-ffff-ahchbh999911"; + /* Too long uuid string */ + const char *uuid_incorrect_3 = "a7a38502-7465-9cbd-98ea-73003906dad5dd"; + /* Too short uuid string */ + const char *uuid_incorrect_4 = "72abd839-7109-64bd-cfef-a8266"; + + assert_int_equal(-1, parse_uuid(uuid_buf, uuid_incorrect_1)); + assert_int_equal(-1, parse_uuid(uuid_buf, uuid_incorrect_2)); + assert_int_equal(-1, parse_uuid(uuid_buf, uuid_incorrect_3)); + assert_int_equal(-1, parse_uuid(uuid_buf, uuid_incorrect_4)); +} + +static void test_guid(void **state) +{ + guid_t guid = GUID_INIT(0x1F4D66BB, 0xDEAD, 0xBEEF, + 0x08, 0xAB, 0x21, 0x37, 0xBB, 0x07, 0xDD, 0x4C); + guid_t guid_copy; + const guid_t guid_bin = { { + 0xBB, 0x66, 0x4D, 0x1F, + 0xAD, 0xDE, + 0xEF, 0xBE, + 0x08, 0xAB, 0x21, 0x37, 0xBB, 0x07, 0xDD, 0x4C + } }; + + /* GUID produced using GUID_INIT() macro should be identical to guid_bin + Check it by comparing memory directly and using provided comparison function */ + assert_memory_equal(guid.b, guid_bin.b, UUID_LEN); + assert_int_equal(0, guidcmp(&guid, &guid_bin)); + + /* Copy GUID and compare it with original */ + guidcpy(&guid_copy, &guid); + assert_memory_equal(guid.b, guid_copy.b, UUID_LEN); + assert_int_equal(0, guidcmp(&guid, &guid_copy)); + + /* Binary negate bits of one of GUIDs bytes. + Expect comparison to fail as GUIDs should differ */ + guid_copy.b[7] = ~guid_copy.b[7]; + assert_int_not_equal(0, guidcmp(&guid, &guid_copy)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_parse_uuid_correct), + cmocka_unit_test(test_parse_uuid_incorrect), + cmocka_unit_test(test_guid), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/51976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f8498ad3d9d0d68b34aa0b48daca60545ec3f4e Gerrit-Change-Number: 51976 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48671 ) Change subject: mb/ocp/tiogapass: use IPMI driver functionality for "POST complete" ...................................................................... mb/ocp/tiogapass: use IPMI driver functionality for "POST complete" Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/ramstage.c 2 files changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 8504438..a9bfe7f 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -49,6 +49,7 @@ end device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 on end # Host bridge device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers @@ -77,8 +78,11 @@ device pci 1f.0 on chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + use pch_gpio as gpio_dev register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "90" + register "post_complete_gpio" = "GPP_B20" + register "post_complete_invert" = "1" end chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index df77205..1439c3b 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -3,9 +3,7 @@ #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> -#include <gpio.h> #include <soc/ramstage.h> -#include <soc/lewisburg_pch_gpio_defs.h> extern struct fru_info_str fru_strings; @@ -136,12 +134,6 @@ { } -static void pull_post_complete_pin(void *unused) -{ - /* Pull Low post complete pin */ - gpio_output(GPP_B20, 0); -} - #if CONFIG(GENERATE_SMBIOS_TABLES) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -189,5 +181,3 @@ .enable_dev = mainboard_enable, .final = mainboard_final, }; - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/48671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Gerrit-Change-Number: 48671 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/tiogapass: correct "POST complete" pad initial value
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48670 ) Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value ...................................................................... mb/ocp/tiogapass: correct "POST complete" pad initial value On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST complete" to the BMC. According to the schematics and the code in `ramstage.c`, the signal is active-low. There is an external pull-up resistor. To make the signalling work as it should, set the initial output value to `high`. Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 97ab7cb..59ab3e7 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -99,7 +99,7 @@ /* GPP_B19 - GPIO */ PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPP_B20 - GPIO */ - PAD_CFG_GPO(GPP_B20, 0, DEEP), + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPP_B21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Gerrit-Change-Number: 48670 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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