coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/i440bx: Enable bootblock console
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41461 ) Change subject: nb/intel/i440bx: Enable bootblock console ...................................................................... nb/intel/i440bx: Enable bootblock console Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41461/1 diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 8a6783e..d51cc0c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -4,7 +4,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select NO_BOOTBLOCK_CONSOLE config SDRAMPWR_4DIMM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/41461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18 Gerrit-Change-Number: 41461 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2b: Add option table support
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41560 ) Change subject: mb/asus/p2b: Add option table support ...................................................................... mb/asus/p2b: Add option table support Just do it already. The two SCSI-specific options for p2b-{ls,ds} will be wired up in a followup. They will be ignored by other boards without the hardware. Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig A src/mainboard/asus/p2b/cmos.default A src/mainboard/asus/p2b/cmos.layout 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41560/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f21de71..762207c 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -17,6 +17,7 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 + select HAVE_OPTION_TABLE select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS diff --git a/src/mainboard/asus/p2b/cmos.default b/src/mainboard/asus/p2b/cmos.default new file mode 100644 index 0000000..447726f --- /dev/null +++ b/src/mainboard/asus/p2b/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Enable +udma_enable=Enable +scsi_lvd_term=Enable +scsi_se_term=Enable diff --git a/src/mainboard/asus/p2b/cmos.layout b/src/mainboard/asus/p2b/cmos.layout new file mode 100644 index 0000000..5fd379f --- /dev/null +++ b/src/mainboard/asus/p2b/cmos.layout @@ -0,0 +1,74 @@ +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +#409 2 e 5 power_on_after_fail +411 1 e 1 udma_enable + +# ----------------------------------------------------------------- +# p2b-[ld]s config options: onboard SCSI termination +# Controls PIIX4 GPO22 (Ultra2-68) and GPO23 (SCSI-50) +412 1 e 1 scsi_se_term +413 1 e 2 scsi_lvd_term + +# ----------------------------------------------------------------- +# TODO: raminit config options +#415 1 e 6 ram_timing +#416 1 e 5 srp_timing +#417 1 e 5 srcd_timing +#418 1 e 5 cas_latency + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable +# Inverted on/off enum +2 0 Enable +2 1 Disable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +#5 0 3 +#5 1 2 + +#6 0 Auto +#6 1 Manual + +checksums + +checksum 592 975 976 + + -- To view, visit https://review.coreboot.org/c/coreboot/+/41560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Gerrit-Change-Number: 41560 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Provide readXp/writeXp helpers in arch/mmio.h
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51862 ) Change subject: arch/x86: Provide readXp/writeXp helpers in arch/mmio.h ...................................................................... arch/x86: Provide readXp/writeXp helpers in arch/mmio.h These p-suffixed helpers allow dropping pointer casts in call-sites, which is particularly useful when accessing registers at an offset from a base address. Move existing helpers in chipset code to arch/mmio.h and create the rest accordingly. Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/mmio.h M src/northbridge/intel/ironlake/raminit.c M src/southbridge/intel/bd82x6x/early_thermal.c 3 files changed, 40 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index c2aa0fb..7188eac 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -45,4 +45,44 @@ *((volatile uint64_t *)(addr)) = value; } +static __always_inline uint8_t read8p(const uintptr_t addr) +{ + return read8((void *)addr); +} + +static __always_inline uint16_t read16p(const uintptr_t addr) +{ + return read16((void *)addr); +} + +static __always_inline uint32_t read32p(const uintptr_t addr) +{ + return read32((void *)addr); +} + +static __always_inline uint64_t read64p(const uintptr_t addr) +{ + return read64((void *)addr); +} + +static __always_inline void write8p(const uintptr_t addr, const uint8_t value) +{ + write8((void *)addr, value); +} + +static __always_inline void write16p(const uintptr_t addr, const uint16_t value) +{ + write16((void *)addr, value); +} + +static __always_inline void write32p(const uintptr_t addr, const uint32_t value) +{ + write32((void *)addr, value); +} + +static __always_inline void write64p(const uintptr_t addr, const uint64_t value) +{ + write64((void *)addr, value); +} + #endif /* __ARCH_MMIO_H__ */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 34e5657..af835e2 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -115,16 +115,6 @@ return val; } -static void write32p(uintptr_t addr, uint32_t val) -{ - write32((void *)addr, val); -} - -static uint32_t read32p(uintptr_t addr) -{ - return read32((void *)addr); -} - static void sfence(void) { asm volatile ("sfence"); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index d005135..32ad3c2 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -6,21 +6,6 @@ #include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> -static void write8p(uintptr_t addr, uint8_t val) -{ - write8((uint8_t *)addr, val); -} - -static void write16p(uintptr_t addr, uint16_t val) -{ - write16((uint16_t *)addr, val); -} - -static uint16_t read16p(uintptr_t addr) -{ - return read16((uint16_t *)addr); -} - /* Temporary address for the thermal BAR */ #define TBARB_TEMP 0x40000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/51862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Gerrit-Change-Number: 51862 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/i82371eb: Claim less I/O ports in ACPI
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41093 ) Change subject: sb/intel/i82371eb: Claim less I/O ports in ACPI ...................................................................... sb/intel/i82371eb: Claim less I/O ports in ACPI To avoid resource conflicts, this change leaves unclaimed: - PM and SMBus ports (claimed by MBRS device written in SSDT) - Ports 0x2e-0x2f (After reviewing Asus P3B-F OEM firmware) Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 1 file changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41093/1 diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 8b60edb..45e7a5e 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -31,15 +31,13 @@ { Name (BUF1, ResourceTemplate () { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) /* PIIX4E ports */ /* Aliased DMA ports */ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) /* Aliased timer ports */ IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) @@ -49,18 +47,10 @@ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + /* W83977TF/EF Super I/O config ports */ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) Return (BUF1) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/41093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Gerrit-Change-Number: 41093 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Ensure MCH has acked raminit
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51940 ) Change subject: nb/intel/haswell: Ensure MCH has acked raminit ...................................................................... nb/intel/haswell: Ensure MCH has acked raminit Haswell MRC.bin can return zero even when raminit did not complete successfully. When this happens, the memory controller will not have acknowledged raminit: the mc_init_done_ack bit in the MC_INIT_STATE_G register will be zero, and memory accesses will lock up the system. To handle this situation more gracefully, check the mc_init_done_ack bit after running MRC. If the bit is not set, log a fatal error and halt. Tested on Asrock B85M Pro4: - With badly-seated DIMMs, MRC raminit fails and coreboot dies. - After reseating the DIMMs, the board still boots successfully. Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 5da1129..ff2456b 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -169,6 +169,16 @@ (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, (version >> 0) & 0xff); + /* + * MRC may return zero even when raminit did not complete successfully. + * Ensure the mc_init_done_ack bit is set before continuing. Otherwise, + * attempting to access memory will lock up the system. + */ + if (!(MCHBAR32(MC_INIT_STATE_G) & (1 << 5))) { + printk(BIOS_EMERG, "Memory controller did not acknowledge raminit.\n"); + die("MRC raminit failed\n"); + } + report_memory_config(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d Gerrit-Change-Number: 51940 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/*/smihandler.c: Correct BIOS_CNTL access width
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51939 ) Change subject: sb/intel/*/smihandler.c: Correct BIOS_CNTL access width ...................................................................... sb/intel/*/smihandler.c: Correct BIOS_CNTL access width The BIOS_CNTL register is 8 bits wide on all affected platforms. Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 4279eb8..733c625 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -374,7 +374,7 @@ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -388,7 +388,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index c2f34ab..9c7b269 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -348,7 +348,7 @@ // BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); + u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL); if (bios_cntl & 1) { /* @@ -362,7 +362,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Gerrit-Change-Number: 51939 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Disable GFX
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51928 ) Change subject: mb/google/guybrush: Disable GFX ...................................................................... mb/google/guybrush: Disable GFX This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index f5f9018..7ca9175 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -48,7 +48,8 @@ device ref gpp_bridge_3 on end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - device ref gfx on end # Internal GPU (GFX) + # b/183971103 - We can't enable GFX because it locks up the OS + device ref gfx off end # Internal GPU (GFX) device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/51928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Gerrit-Change-Number: 51928 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/nau8825: Support nau8825 for ACPI GPIO descriptors
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51922 ) Change subject: drivers/i2c/nau8825: Support nau8825 for ACPI GPIO descriptors ...................................................................... drivers/i2c/nau8825: Support nau8825 for ACPI GPIO descriptors Add definitions to describe GPIOs in generated ACPI objects. The method allow either write a GpioInt() or Interrupt() descriptor. Signed-off-by: Seven Lee <wtli(a)nuvoton.com> Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51922 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/i2c/nau8825/chip.h M src/drivers/i2c/nau8825/nau8825.c 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/drivers/i2c/nau8825/chip.h b/src/drivers/i2c/nau8825/chip.h index 9ba1d94..5b160c8 100644 --- a/src/drivers/i2c/nau8825/chip.h +++ b/src/drivers/i2c/nau8825/chip.h @@ -11,6 +11,7 @@ struct drivers_i2c_nau8825_config { /* Interrupt configuration */ struct acpi_irq irq; + struct acpi_gpio irq_gpio; /* I2C Bus Frequency in Hertz (default 400kHz) */ unsigned int bus_speed; diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index a0769d0..01b1f35 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -47,7 +47,11 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); - acpi_device_write_interrupt(&config->irq); + /* Allow either GpioInt() or Interrupt() */ + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); acpigen_write_resourcetemplate_footer(); /* Device Properties */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409 Gerrit-Change-Number: 51922 Gerrit-PatchSet: 2 Gerrit-Owner: leeweitse_seven <WTLI(a)nuvoton.com> Gerrit-Reviewer: David Lin <CTLIN0(a)nuvoton.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Hsu <KCHSU0(a)nuvoton.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/cbnt: Fix ibbhash command line
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51974 ) Change subject: security/intel/cbnt: Fix ibbhash command line ...................................................................... security/intel/cbnt: Fix ibbhash command line Using brackets here seems to break the build for _some_ environments. Removing the brackets fixes it and works just fine. Change-Id: I965b0356337fe74281e7f410fd2bf95c9d96ea93 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51974 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/cbnt/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Deomid "rojer" Ryabkov: Looks good to me, but someone else must approve diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 788b1b7..0eea0a7 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -49,7 +49,7 @@ --pbet=$(CONFIG_INTEL_CBNT_PBET) \ --ibbflags=$(CONFIG_INTEL_CBNT_IBB_FLAGS) \ --entrypoint=$(shell printf "%d" 0xfffffff0) \ - --ibbhash={11,4,12} \ + --ibbhash=11,4,12 \ --ibbsegbase=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_C_ENV_BOOTBLOCK_SIZE)) 1) \ --ibbsegsize=$(shell printf "%d" $(CONFIG_C_ENV_BOOTBLOCK_SIZE)) \ --ibbsegflag=0 \ -- To view, visit https://review.coreboot.org/c/coreboot/+/51974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965b0356337fe74281e7f410fd2bf95c9d96ea93 Gerrit-Change-Number: 51974 Gerrit-PatchSet: 3 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Support LTE module
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51844 ) Change subject: mb/google/dedede/var/cret: Support LTE module ...................................................................... mb/google/dedede/var/cret: Support LTE module Add LTE module support into devicetree and associated GPIO configuration. BUG=b:183774169 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I14684bb30e46bf845a401649f56b16b60db379e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51844 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/cret/Makefile.inc M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb A src/mainboard/google/dedede/variants/cret/variant.c 4 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/Makefile.inc b/src/mainboard/google/dedede/variants/cret/Makefile.inc index eb2c9bc..fd60a18 100644 --- a/src/mainboard/google/dedede/variants/cret/Makefile.inc +++ b/src/mainboard/google/dedede/variants/cret/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c index cb56221..3dd15ef 100644 --- a/src/mainboard/google/dedede/variants/cret/gpio.c +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -5,6 +5,8 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), /* C12 : AP_PEN_DET_ODL ==> NC */ PAD_NC(GPP_C12, UP_20K), /* C18 : AP_I2C_EMR_SDA */ @@ -13,6 +15,8 @@ PAD_NC(GPP_C19, NONE), /* C22 : UART2_RTS_N ==> NC */ PAD_NC(GPP_C22, UP_20K), + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D12 : WCAM_RST_L ==> NC */ PAD_NC(GPP_D12, NONE), /* D14 : EN_PP1200_CAMERA ==> NC */ @@ -23,6 +27,8 @@ PAD_NC(GPP_D19, NONE), /* D20 : WWAN_WLAN_COEX2 ==> NC */ PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), /* E0 : CLK_24M_UCAM ==> NC */ PAD_NC(GPP_E0, NONE), /* E2 : CLK_24M_WCAM ==> NC */ @@ -33,6 +39,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL ==> NC */ PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* G0 : SD_CMD ==> NC */ PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 ==> NC */ diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 45e7afb..0cf3bdf 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -75,6 +75,13 @@ chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" device usb 3.3 on end end end diff --git a/src/mainboard/google/dedede/variants/cret/variant.c b/src/mainboard/google/dedede/variants/cret/variant.c new file mode 100644 index 0000000..2540fc7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cret/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/51844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14684bb30e46bf845a401649f56b16b60db379e8 Gerrit-Change-Number: 51844 Gerrit-PatchSet: 6 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021