coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Michał Żygowski, Angel Pons, Patrick Rudolph, Piotr Król. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52101 ) Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Gerrit-Change-Number: 52101 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 07:59:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52100 ) Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52100/comment/e8086ee1_b618b6b4 PS1, Line 13: . > Hmmmmm... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Gerrit-Change-Number: 52100 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 07:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Drop unreferenced `InternalGfx`
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52104 ) Change subject: soc/intel/alderlake: Drop unreferenced `InternalGfx` ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > Sorry, I still don't get what you mean. This is the UPD field: […] ... sorry, my fault. -- To view, visit https://review.coreboot.org/c/coreboot/+/52104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Gerrit-Change-Number: 52104 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 07:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP
by Paul Menzel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Frank Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52127 ) Change subject: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52127/comment/7244d46c_796a3859 PS1, Line 9: Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180. Why is the new ACPI name needed? (Please refer to the Linux kernel changes, if that is related.) Please always summarize the bug report in the commit message, as not all folks are granted access. -- To view, visit https://review.coreboot.org/c/coreboot/+/52127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Gerrit-Change-Number: 52127 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 07:54:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Add date to the toolchain revision
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48901 ) Change subject: util/crossgcc: Add date to the toolchain revision ...................................................................... util/crossgcc: Add date to the toolchain revision With the current version method, it's not possible to determine if a different version is older or newer than the current version without digging into the repository and finding the dates for the version numbers. This change adds the commit date to the start of the toolchain version which will let us tell at a glance how old or new the toolchain is. It's not perfect because multiple toolchain commits can go in on the same day, but adding the time made the string even longer, and really doesn't help that much. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c --- M util/crossgcc/Makefile.inc M util/crossgcc/buildgcc 2 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48901/1 diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 74de5bd..f032964 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -54,7 +54,7 @@ test-toolchain: ifeq ($(COMPILER_OUT_OF_DATE),1) echo "The coreboot toolchain is not the current version." - $(error ) + $(error Halting) else echo "The coreboot toolchain is the current version." endif # ifeq ($(COMPILER_OUT_OF_DATE),1) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5af3d5a..25b0d27 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -16,8 +16,7 @@ cd "$(dirname "$0")" || exit 1 -CROSSGCC_DATE="$(git log -n 1 --pretty=%ad --date=short .)" -CROSSGCC_VERSION="$(git log -n 1 --pretty=%h .)" +CROSSGCC_VERSION="$(git log -n 1 --pretty=%ad --date=short .)_$(git log -n 1 --pretty=%h .)" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -591,7 +590,7 @@ } printversion() { - printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n" + printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ${NC}\n\n" } myversion() @@ -728,7 +727,7 @@ ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ --with-gmp="$DESTDIR$TARGETDIR" --with-mpfr="$DESTDIR$TARGETDIR" \ --with-mpc="$DESTDIR$TARGETDIR" \ - --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION" \ && \ # shellcheck disable=SC2086 $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ @@ -774,7 +773,7 @@ --with-gmp="$DESTDIR$TARGETDIR" --with-mpfr="$DESTDIR$TARGETDIR" \ --with-mpc="$DESTDIR$TARGETDIR" \ --with-gnu-as --with-gnu-ld \ - --with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + --with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION" \ && \ mkdir -p gcc/$TARGETARCH && \ ln -s "$DESTDIR$TARGETDIR/$TARGETARCH/bin" "gcc/$TARGETARCH/$GCC_VERSION" && \ @@ -842,7 +841,7 @@ test "$UNAME" = "FreeBSD" && HOST="_FreeBSD" test "$UNAME" = "Cygwin" && HOST="_CYGWIN" HOST="$HOST" CFLAGS="$CFLAGS" \ - OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE\"' " \ + OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION\"' " \ $MAKE $JOBS CC="$(hostcc host)" iasl acpibin acpidump acpiexec acpihelp acpisrc acpixtract rm -f "$DESTDIR$TARGETDIR/bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpisrc,acpixtract}" || touch "$RDIR/.failed" cp bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpisrc,acpixtract} "$DESTDIR$TARGETDIR/bin" || touch "$RDIR/.failed" @@ -857,7 +856,7 @@ cd - || exit 1 $CMAKE -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX="$DESTDIR$TARGETDIR" \ - -DCLANG_VENDOR="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE - " \ + -DCLANG_VENDOR="coreboot toolchain v$CROSSGCC_VERSION - " \ -DCMAKE_BUILD_TYPE=Release ../$LLVM_DIR || touch .failed # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed -- To view, visit https://review.coreboot.org/c/coreboot/+/48901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c Gerrit-Change-Number: 48901 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Allow TPM initialization
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52052 ) Change subject: mb/facebook/monolith: Allow TPM initialization ...................................................................... mb/facebook/monolith: Allow TPM initialization TPM_INIT is disabled by default. This prevents TPM to be operational when VBOOT is disabled. Remove the TPM_INIT disable. BUG=N/A TEST=tested on facebook monolith with VBOOT disabled. Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/monolith/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 1962352..fe3b056 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -68,10 +68,6 @@ int default 2 -config TPM_INIT - bool - default n - config MAINBOARD_SUPPORTS_SKYLAKE_CPU bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/52052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d Gerrit-Change-Number: 52052 Gerrit-PatchSet: 3 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/facebook/monolith: Update VBOOT settings
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52053 ) Change subject: mb/facebook/monolith: Update VBOOT settings ...................................................................... mb/facebook/monolith: Update VBOOT settings Make sure the standard for the board options are set when VBOOT is enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/monolith/Kconfig 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index ddbc27e..1962352 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -80,14 +80,15 @@ bool default n +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SLOTS_RW_A + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_ENABLE_CBFS_FALLBACK + config RW_REGION_ONLY string "Files in RW only" -config VBOOT_ENABLE_CBFS_FALLBACK - bool - default y - depends on VBOOT - config VBOOT_ALWAYS_ALLOW_UDC def_bool y depends on VBOOT && !CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/52053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337 Gerrit-Change-Number: 52053 Gerrit-PatchSet: 2 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50138 ) Change subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M ...................................................................... soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/lpc/lpc.c 4 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Ronak Kanabar: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3382df..520d403 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3037,6 +3037,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 /* Intel PCIE device ids */ @@ -3808,6 +3809,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 +#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index e3646e0..2666426 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,6 +23,7 @@ const char *name; } cpu_table[] = { { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, + { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" }, }; static struct { @@ -78,6 +79,7 @@ { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" }, }; static struct { @@ -96,6 +98,7 @@ { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ca96f35..0920a05 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -296,6 +296,7 @@ PCI_DEVICE_ID_INTEL_ADL_GT1_9, PCI_DEVICE_ID_INTEL_ADL_P_GT2, PCI_DEVICE_ID_INTEL_ADL_S_GT1, + PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index df34f3f..e22518c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -329,6 +329,7 @@ PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, PCI_DEVICE_ID_INTEL_SPR_ESPI_1, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Gerrit-Change-Number: 50138 Gerrit-PatchSet: 25 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Dana Alkattan <dana.alkattan(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay...
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51739 ) Change subject: mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 ms ...................................................................... mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 ms 1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. BUG=b:181711141 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51739 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 3140b85..139cd99 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -103,8 +103,8 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - # Parameter T3 >= 10ms - register "generic.reset_delay_ms" = "120" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/51739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Gerrit-Change-Number: 51739 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: Lindar/Lillipup: Enable Bayhub SD card reader power-saving mode
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51623 ) Change subject: Lindar/Lillipup: Enable Bayhub SD card reader power-saving mode ...................................................................... Lindar/Lillipup: Enable Bayhub SD card reader power-saving mode Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup. BUG=b:173676531 TEST=Boot to OS and test with SD card function. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 4702832..4b580ad 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -20,6 +20,7 @@ select INTEL_CAR_NEM select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 + select DRIVERS_GENERIC_BAYHUB_LV2 config BOARD_GOOGLE_MALEFOR bool "-> Malefor" -- To view, visit https://review.coreboot.org/c/coreboot/+/51623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Gerrit-Change-Number: 51623 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit April 2021