coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48671 ) Change subject: mb/ocp/tiogapass: use IPMI driver functionality for "POST complete" ...................................................................... mb/ocp/tiogapass: use IPMI driver functionality for "POST complete" Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/ramstage.c 2 files changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 8504438..a9bfe7f 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -49,6 +49,7 @@ end device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 on end # Host bridge device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers @@ -77,8 +78,11 @@ device pci 1f.0 on chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + use pch_gpio as gpio_dev register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "90" + register "post_complete_gpio" = "GPP_B20" + register "post_complete_invert" = "1" end chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index df77205..1439c3b 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -3,9 +3,7 @@ #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> -#include <gpio.h> #include <soc/ramstage.h> -#include <soc/lewisburg_pch_gpio_defs.h> extern struct fru_info_str fru_strings; @@ -136,12 +134,6 @@ { } -static void pull_post_complete_pin(void *unused) -{ - /* Pull Low post complete pin */ - gpio_output(GPP_B20, 0); -} - #if CONFIG(GENERATE_SMBIOS_TABLES) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -189,5 +181,3 @@ .enable_dev = mainboard_enable, .final = mainboard_final, }; - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/48671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Gerrit-Change-Number: 48671 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/tiogapass: correct "POST complete" pad initial value
by Michael Niewöhner (Code Review) 06 Apr '21

06 Apr '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48670 ) Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value ...................................................................... mb/ocp/tiogapass: correct "POST complete" pad initial value On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST complete" to the BMC. According to the schematics and the code in `ramstage.c`, the signal is active-low. There is an external pull-up resistor. To make the signalling work as it should, set the initial output value to `high`. Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 97ab7cb..59ab3e7 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -99,7 +99,7 @@ /* GPP_B19 - GPIO */ PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPP_B20 - GPIO */ - PAD_CFG_GPO(GPP_B20, 0, DEEP), + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPP_B21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Gerrit-Change-Number: 48670 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/tpm/Kconfig: TPM_INIT for measured boot only
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52050 ) Change subject: drivers/tpm/Kconfig: TPM_INIT for measured boot only ...................................................................... drivers/tpm/Kconfig: TPM_INIT for measured boot only TPM_INIT depends on VBOOT but should also depend on VENDORCODE_ELTAN_xBOOT. Add dependency. TPM_INIT will be enable for measured boot only. BUG = NA TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured boot and eltan security. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/drivers/tpm/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Wim Vervoorn: Looks good to me, approved diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index baf760b..d8a1e10 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -1,7 +1,7 @@ config TPM_INIT bool default y if TPM1 || TPM2 - depends on !VBOOT + depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. -- To view, visit https://review.coreboot.org/c/coreboot/+/52050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb Gerrit-Change-Number: 52050 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/cbfsglue.h: Use BIOS_INFO for LOG macro
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52019 ) Change subject: include/cbfsglue.h: Use BIOS_INFO for LOG macro ...................................................................... include/cbfsglue.h: Use BIOS_INFO for LOG macro The ERROR() and LOG() macros both used BIOS_ERR as the error level. The messages generated by the LOG() macro are informational items. Change to BIOS_INFO to reflect that. BUG=N/A TEST=tested on facebook monolith Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/include/cbfs_glue.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved Frans Hendriks: Looks good to me, approved diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h index ffca83e..3170c37 100644 --- a/src/include/cbfs_glue.h +++ b/src/include/cbfs_glue.h @@ -20,7 +20,7 @@ (CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE)) #define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) -#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#define LOG(...) printk(BIOS_INFO, "CBFS: " __VA_ARGS__) #define DEBUG(...) do { \ if (CONFIG(DEBUG_CBFS)) \ printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/52019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Gerrit-Change-Number: 52019 Gerrit-PatchSet: 2 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/shadowmountain: Add Cr50 support
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51086 ) Change subject: mb/intel/shadowmountain: Add Cr50 support ...................................................................... mb/intel/shadowmountain: Add Cr50 support This patch includes changes to add Cr50 support over GSPI0. BUG=b:175579964 TEST=Verify TPM init is done and boots to kernel Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 2 files changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rizwan Qureshi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index a8f7bf5..e42160f 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -20,6 +20,8 @@ select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE select SOC_INTEL_CSE_LITE_SKU @@ -34,7 +36,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE config DIMM_SPD_SIZE @@ -69,4 +70,11 @@ hex default 0x1c000000 # 448 MiB +config DRIVER_TPM_SPI_BUS + default 0x1 + +config TPM_TIS_ACPI_INTERRUPT + int + default 3 # GPE0_DW0_3 (GPP_C3) + endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 98f6400..8b31784 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -311,7 +311,14 @@ device pci 1d.3 off end # RP12 device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 - device pci 1e.2 on end # GSPI0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)" + device spi 0 on end + end + end # GSPI0 device pci 1e.3 off end # GSPI1 device pci 1f.0 on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/51086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Gerrit-Change-Number: 51086 Gerrit-PatchSet: 8 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: src/arch/smbios.c: Allow mainboard to fill Vendor name
by Meera Ravindranath (Code Review) 06 Apr '21

06 Apr '21

Meera Ravindranath has restored this change. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: src/arch/smbios.c: Allow mainboard to fill Vendor name ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: restore

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Change in coreboot[master]: util/kconfig_lint: Drop exception for paths without quotes
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52066 ) Change subject: util/kconfig_lint: Drop exception for paths without quotes ...................................................................... util/kconfig_lint: Drop exception for paths without quotes The tree is clean at the moment. Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/lint/kconfig_lint 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 2341976..43a3ca6 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -993,11 +993,6 @@ handle_expressions( $1, $inside_config, $filename, $line_no ); handle_expressions( $2, $inside_config, $filename, $line_no ); } - - # work around kconfig spec violation for now - paths not in quotes - elsif ( $exprline =~ /^\s*([A-Za-z0-9_\-\/]+)\s*$/ ) { # <symbol> (1) - return; - } else { show_error("Unrecognized expression '$exprline' in $filename line $line_no."); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc Gerrit-Change-Number: 52066 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/msi/h81m-p33: Put MAINBOARD_DIR in double quotes
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52065 ) Change subject: mb/msi/h81m-p33: Put MAINBOARD_DIR in double quotes ...................................................................... mb/msi/h81m-p33: Put MAINBOARD_DIR in double quotes Change-Id: I73160985c025cb0945a4ac16c8c3ebb988d3858f Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52065 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/msi/h81m-p33/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig index 185c340..de21a55 100644 --- a/src/mainboard/msi/h81m-p33/Kconfig +++ b/src/mainboard/msi/h81m-p33/Kconfig @@ -17,7 +17,7 @@ config MAINBOARD_DIR string - default msi/h81m-p33 + default "msi/h81m-p33" config MAINBOARD_PART_NUMBER string -- To view, visit https://review.coreboot.org/c/coreboot/+/52065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73160985c025cb0945a4ac16c8c3ebb988d3858f Gerrit-Change-Number: 52065 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Move early GPIO config earlier
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52062 ) Change subject: mb/google/brya: Move early GPIO config earlier ...................................................................... mb/google/brya: Move early GPIO config earlier The recent refactor of console UART GPIOs to mainboard's bootblock caused brya boards to lose the first ~5 lines of the logs from bootblock. Rename bootblock_mainboard_init to bootblock_mainboard_early_init so that the UART pads will be ready by the time the console is initialized. BUG=b:184319828 TEST=First lines from report_platform.c are now seen in UART output Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index 817dd0f..1815615 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <bootblock_common.h> -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; -- To view, visit https://review.coreboot.org/c/coreboot/+/52062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Gerrit-Change-Number: 52062 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: Add obvious definition for `calloc`
by Patrick Georgi (Code Review) 06 Apr '21

06 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51949 ) Change subject: lib: Add obvious definition for `calloc` ...................................................................... lib: Add obvious definition for `calloc` The calloc() function is useful in addition to malloc and friends, so add the obvious definition. Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/stdlib.h M src/lib/malloc.c M tests/lib/malloc-test.c 3 files changed, 34 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/stdlib.h b/src/include/stdlib.h index f6369bf..8636ea4 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -5,6 +5,7 @@ void *memalign(size_t boundary, size_t size); void *malloc(size_t size); +void *calloc(size_t nitems, size_t size); void free(void *ptr); #endif /* STDLIB_H */ diff --git a/src/lib/malloc.c b/src/lib/malloc.c index cd86f99..7d787d6 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -1,5 +1,6 @@ -#include <stdlib.h> #include <console/console.h> +#include <stdlib.h> +#include <string.h> #if CONFIG(DEBUG_MALLOC) #define MALLOCDBG(x...) printk(BIOS_SPEW, x) @@ -54,6 +55,15 @@ return memalign(sizeof(u64), size); } +void *calloc(size_t nitems, size_t size) +{ + void *p = malloc(nitems * size); + if (p) + memset(p, 0, nitems * size); + + return p; +} + void free(void *ptr) { if (ptr == NULL) diff --git a/tests/lib/malloc-test.c b/tests/lib/malloc-test.c index e358fff..fefacbb 100644 --- a/tests/lib/malloc-test.c +++ b/tests/lib/malloc-test.c @@ -2,6 +2,7 @@ /* Include malloc() and memalign() source code and alter its name to indicate the functions source origin. */ +#define calloc cb_calloc #define malloc cb_malloc #define free cb_free #define memalign cb_memalign @@ -10,6 +11,7 @@ #include "../lib/malloc.c" +#undef calloc #undef malloc #undef free #undef memalign @@ -46,6 +48,12 @@ return 0; } +static int setup_calloc_test(void **state) +{ + memset(&_heap, 0xFF, TEST_HEAP_SZ); + return setup_test(state); +} + static void test_malloc_out_of_memory(void **state) { /* Expect die() call if out of memory */ @@ -130,6 +138,19 @@ } } +static void test_calloc_memory_is_zeroed(void **state) +{ + const size_t nitems = 42; + const size_t size = sizeof(uint32_t); + void *ptr = cb_calloc(nitems, size); + assert_non_null(ptr); + + for (size_t i = 0; i < nitems; i++) { + const uint32_t *p = (const uint32_t *)ptr + i; + assert_int_equal(*p, 0); + } +} + int main(void) { const struct CMUnitTest tests[] = { @@ -140,6 +161,7 @@ cmocka_unit_test_setup(test_memalign_out_of_memory, setup_test), cmocka_unit_test_setup(test_memalign_zero, setup_test), cmocka_unit_test_setup(test_memalign_multiple_small_allocations, setup_test), + cmocka_unit_test_setup(test_calloc_memory_is_zeroed, setup_calloc_test), }; return cmocka_run_group_tests(tests, NULL, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/51949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Gerrit-Change-Number: 51949 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021