coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Documentation/mb/ocp: Update Delta Lake documentation
by Jonathan Zhang (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Paul Menzel, Stefan Reinauer, Sumeet R Pawnikar, Angel Pons, ron minnich, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51824 ) Change subject: Documentation/mb/ocp: Update Delta Lake documentation ...................................................................... Patch Set 7: (1 comment) File Documentation/mainboard/ocp/deltalake.md: https://review.coreboot.org/c/coreboot/+/51824/comment/73fc4ee4_492a868f PS7, Line 66: other coreboot > Does this header file still contain DeltaLake VPDs ? Yes, it does. All the VPDs mentioned in this section apply to DeltaLake, the explicitly listed one are used by Linuxboot. The rest affects coreboot; they are listed in src/mainboard/ocp/deltalake/vpd.h. -- To view, visit https://review.coreboot.org/c/coreboot/+/51824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf Gerrit-Change-Number: 51824 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards
by Aaron Durbin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Aseda Aboagye, Karthik Ramasubramanian. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/52147/comment/69cbae83_763c9a91 PS1, Line 38: HECI_DISABLE_USING_SMM > I am fine with leaving HECI interface enabled. That will be one less diff between Cr50 and TPM2.0. […] Why would we need to keep this in Kconfig based on your suggestion? >-------if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) >------->-------heci_disable(); Wouldn't removing the Kcofnig make it entirely driven by devicetree? -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards
by Karthik Ramasubramanian (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Aseda Aboagye, Aaron Durbin. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/52147/comment/53983ae6_15e3600f PS1, Line 38: HECI_DISABLE_USING_SMM > An argument can be made for keeping things the way they were as well as consistency everywhere. […] I am fine with leaving HECI interface enabled. That will be one less diff between Cr50 and TPM2.0. How about we retain this in SoC Kconfig and enable HECI in devicetree("config->HeciEnabled = 1" ). That will allow us to enable the HECI interface for all dedede variants. Also if we see any problem in the future, we can override in the individual variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 17:59:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 ) Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/51846/comment/59206496_893e1a11 PS2, Line 316: /* : * SLP_S3 Minimum Assertion Width Policy : * 1 = 60us : * 2 = 1ms : * 3 = 50ms (default) : * 4 = 2s : */ : uint8_t PchPmSlpS3MinAssert; : : /* : * SLP_S4 Minimum Assertion Width Policy : * 1 = 1s (default) : * 2 = 2s : * 3 = 3s : * 4 = 4s : */ : uint8_t PchPmSlpS4MinAssert; : : /* : * SLP_SUS Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 500ms : * 3 = 1s : * 4 = 4s (default) : */ : uint8_t PchPmSlpSusMinAssert; : : /* : * SLP_A Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 4s : * 3 = 98ms : * 4 = 2s (default) : */ : uint8_t PchPmSlpAMinAssert; : : /* : * PCH PM Reset Power Cycle Duration : * 0 = 4s (default) : * 1 = 1s : * 2 = 2s : * 3 = 3s : * 4 = 4s : * : * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the : * stretch duration programmed in the following registers: : * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) : * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) : * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) : * - PM_CFG.SLP_LAN_MIN_ASST_WDTH : */ : uint8_t PchPmPwrCycDur; > suggestion: Could we define these all as enums defined in terms of some base unit, like microseconds […] That sounds okay to me. Only thing to be careful about is ensuring you apply the conversion when setting the UPD: ``` if (!config->PchPmSlpS3MinAssert) config->PchPmSlpS3MinAssert = convert_to_upd(SlpS3_MinAssert_50ms); /* Default */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/51846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91bd49d35f80fbde4aa3b7ec816217d2c1a5853e Gerrit-Change-Number: 51846 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 17:58:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 ) Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/51846/comment/98476fe8_8eacc478 PS2, Line 316: /* : * SLP_S3 Minimum Assertion Width Policy : * 1 = 60us : * 2 = 1ms : * 3 = 50ms (default) : * 4 = 2s : */ : uint8_t PchPmSlpS3MinAssert; : : /* : * SLP_S4 Minimum Assertion Width Policy : * 1 = 1s (default) : * 2 = 2s : * 3 = 3s : * 4 = 4s : */ : uint8_t PchPmSlpS4MinAssert; : : /* : * SLP_SUS Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 500ms : * 3 = 1s : * 4 = 4s (default) : */ : uint8_t PchPmSlpSusMinAssert; : : /* : * SLP_A Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 4s : * 3 = 98ms : * 4 = 2s (default) : */ : uint8_t PchPmSlpAMinAssert; : : /* : * PCH PM Reset Power Cycle Duration : * 0 = 4s (default) : * 1 = 1s : * 2 = 2s : * 3 = 3s : * 4 = 4s : * : * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the : * stretch duration programmed in the following registers: : * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) : * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) : * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) : * - PM_CFG.SLP_LAN_MIN_ASST_WDTH : */ : uint8_t PchPmPwrCycDur; suggestion: Could we define these all as enums defined in terms of some base unit, like microseconds? example for Slp_S3#: ``` enum { SlpS3_MinAssert_60us = 60, SlpS3_MinAssert_1ms = 1 * USECS_PER_MSEC, SlpS3_MinAssert_50ms = 50 * USECS_PER_MSEC, SlpS3_MinAssert_2s = 2 * MSECS_PER_USEC * MSECS_PER_SEC } PchPmSlpS3MinAssert; ``` Then if the field is 0 (because it's not used in the devicetree), you set the default in fsp_params.c, e.g.: ``` if (!config->PchPmSlpS3MinAssert) config->PchPmSlpS3MinAssert = SlpS3_MinAssert_50ms; /* Default */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/51846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91bd49d35f80fbde4aa3b7ec816217d2c1a5853e Gerrit-Change-Number: 51846 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 17:49:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
by Michael Niewöhner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52100 ) Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I believe this would be done in CB:51332 actually, it doesn't have to but it may be cleaner that way -- To view, visit https://review.coreboot.org/c/coreboot/+/52100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Gerrit-Change-Number: 52100 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 17:44:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set MSR locks
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Stefan Reinauer, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52160 ) Change subject: soc/intel/xeon_sp: Set MSR locks ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/soc/intel/xeon_sp/Kconfig: https://review.coreboot.org/c/coreboot/+/52160/comment/fc126a88_18124dd9 PS1, Line 39: PARALLEL_MP_AP_WORK remove from tiogapass Kconfig. File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/52160/comment/e4d5e4df_cc7fd844 PS1, Line 146: set_msr_locks This has to happen so late or can it happen during the CPU init? -- To view, visit https://review.coreboot.org/c/coreboot/+/52160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Gerrit-Change-Number: 52160 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 17:15:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by Felix Held (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: ritul guru, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51674 ) Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 10 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 16:18:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by ritul guru (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marshall Dawson, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51674 ) Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... Patch Set 10: Code-Review+1 (4 comments) File src/mainboard/amd/bilby/early_gpio.c: https://review.coreboot.org/c/coreboot/+/51674/comment/72c9dfd4_b40b13dd PS7, Line 22: > nit: remove this extra whitespace here Ack https://review.coreboot.org/c/coreboot/+/51674/comment/42ad3382_8c005fd9 PS7, Line 22: > nit: remove this extra whitespace here Ack File src/mainboard/amd/bilby/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/51674/comment/db7f4ac4_454f6cc3 PS7, Line 73: const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) > I would leave lines 72 and 73 as-is and put the tabs back in. […] Ack https://review.coreboot.org/c/coreboot/+/51674/comment/cec69f7c_1de54123 PS7, Line 73: const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) > I would leave lines 72 and 73 as-is and put the tabs back in. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 10 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 16:16:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by ritul guru (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: ritul guru, Felix Held. Hello build bot (Jenkins), Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51674 to look at the new patch set (#10). Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... mb/amd/bilby: enable boot from NVMe SSD These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/bilby/early_gpio.c M src/mainboard/amd/bilby/gpio.c M src/mainboard/amd/bilby/port_descriptors.c 4 files changed, 48 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51674/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 10 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021