coreboot-gerrit April 2021

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Change in coreboot[master]: mainboard/ocp/deltalake: Add SATA device to device tree
by Jay Talbott (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Stefan Reinauer, Morgan Jang. Jay Talbott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52161 ) Change subject: mainboard/ocp/deltalake: Add SATA device to device tree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6 Gerrit-Change-Number: 52161 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 15:30:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set MSR locks
by Jay Talbott (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Jonathan Zhang, Stefan Reinauer, Patrick Rudolph. Jay Talbott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52160 ) Change subject: soc/intel/xeon_sp: Set MSR locks ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Gerrit-Change-Number: 52160 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 15:29:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google/guybrush/port_descriptors: add dummy descriptors
by Marshall Dawson (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Matt Papageorge, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52141 ) Change subject: [WIP] mb/google/guybrush/port_descriptors: add dummy descriptors ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Are these UNUSED_ENGINE instead and did we default the FSP's UPD to unused? Sorry, I may be confusing behaviors. -- To view, visit https://review.coreboot.org/c/coreboot/+/52141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Gerrit-Change-Number: 52141 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 15:22:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable USB ports in devicetree
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52119 ) Change subject: mb/google/mancomb: Enable USB ports in devicetree ...................................................................... mb/google/mancomb: Enable USB ports in devicetree BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 66 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 305ba0b..b368574 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -46,6 +46,72 @@ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""Rear Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Rear Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""Front Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB HUB"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""Front Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB HUB"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)" + device ref usb2_port6 on end + end + end + end + end end device ref lpc_bridge on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/52119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Gerrit-Change-Number: 52119 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Enable USB ports in devicetree
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Raul Rangel, Mathew King, EricR Lai. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52119 ) Change subject: mb/google/mancomb: Enable USB ports in devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Gerrit-Change-Number: 52119 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 15:17:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable PCIe devices in devicetree
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52118 ) Change subject: mb/google/mancomb: Enable PCIe devices in devicetree ...................................................................... mb/google/mancomb: Enable PCIe devices in devicetree BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index c4ef3f5..305ba0b 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -39,6 +39,11 @@ }" device domain 0 on + device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_1 on end # SD + device ref gpp_bridge_2 on end # LAN + device ref gpp_bridge_3 on end # NVMe + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) end -- To view, visit https://review.coreboot.org/c/coreboot/+/52118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Gerrit-Change-Number: 52118 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Add initial fch irq routing
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52117 ) Change subject: mb/google/mancomb: Add initial fch irq routing ...................................................................... mb/google/mancomb: Add initial fch irq routing BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/mainboard.c 1 file changed, 85 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/mainboard.c b/src/mainboard/google/mancomb/mainboard.c index 2205f8f..5506dfa 100644 --- a/src/mainboard/google/mancomb/mainboard.c +++ b/src/mainboard/google/mancomb/mainboard.c @@ -1,10 +1,91 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/amd_pci_util.h> #include <baseboard/variants.h> #include <device/device.h> +#include <soc/acpi.h> #include <variant/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} guybrush_fch[] = { + { PIRQ_A, PIRQ_NC, PIRQ_NC }, + { PIRQ_B, PIRQ_NC, PIRQ_NC }, + { PIRQ_C, PIRQ_NC, PIRQ_NC }, + { PIRQ_D, PIRQ_NC, PIRQ_NC }, + { PIRQ_E, PIRQ_NC, PIRQ_NC }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, PIRQ_NC }, + { PIRQ_H, PIRQ_NC, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(guybrush_fch); i++) { + entry = guybrush_fch + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +static void pirq_setup(void) +{ + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + static void mainboard_configure_gpios(void) { size_t base_num_gpios, override_num_gpios; @@ -25,6 +106,10 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + + init_tables(); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Gerrit-Change-Number: 52117 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Add eSPI GPIO back to init table
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52123 ) Change subject: mb/google/mancomb: Add eSPI GPIO back to init table ...................................................................... mb/google/mancomb: Add eSPI GPIO back to init table GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 1eb1b80..29fa866 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -108,7 +108,14 @@ /* CLK_REQ0_L */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* GPIO_93 - GPIO_103: Not available */ - /* GPIO_104 - GPIO_108: eSPI configured in early stage */ + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* EGPIO109 */ PAD_NC(GPIO_109), /* GPIO_110 - GPIO_112: Not available */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Gerrit-Change-Number: 52123 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Configure UART0 gpio in early stage
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52122 ) Change subject: mb/google/mancomb: Configure UART0 gpio in early stage ...................................................................... mb/google/mancomb: Configure UART0 gpio in early stage BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 5a6f2ac..1eb1b80 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -166,6 +166,10 @@ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), }; /* GPIO configuration for sleep */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Gerrit-Change-Number: 52122 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARING
by Martin Roth (Code Review) 07 Apr '21

07 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52125 ) Change subject: mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARING ...................................................................... mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARING BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 6a9692c..b681a1e 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -9,6 +9,7 @@ def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select DISABLE_SPI_FLASH_ROM_SHARING select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI -- To view, visit https://review.coreboot.org/c/coreboot/+/52125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Gerrit-Change-Number: 52125 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021