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Change subject: mb/google/dedede/var/boten: Add custom Wifi SAR for botenflex
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
Hi Karthik,
In order to ensure get_wifi_sar_cbfs_filename() be executed, i modify Makefile to change variant.c from smm to ramstage. Does it will impact LTE power on/off behavior? Or i need to do this split initialization in smm and ramstage?
File src/mainboard/google/dedede/variants/boten/variant.c:
https://review.coreboot.org/c/coreboot/+/51501/comment/75202f70_e5f9053c
PS4, Line 32: 0x90000
> Done
Hi Karthik,
In order to ensure get_wifi_sar_cbfs_filename() be executed, i modify Makefile to change variant.c from smm to ramstage. Does it will impact LTE power on/off behavior? Or i need to do this split initialization in smm and ramstage?
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Change subject: soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/amd/bilby: Enable postcode on port 0x80
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/amd/bilby/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/52016/comment/978331d2_89f11e51
PS2, Line 72: const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
need consistent spacing around '*' (ctx:WxO)
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Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
Patch Set 4:
(2 comments)
File src/soc/amd/common/block/pm/Kconfig:
https://review.coreboot.org/c/coreboot/+/51924/comment/ecc44c1a_13ad9619
PS4, Line 5: select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
> nit: Probably add it as: […]
Yeah, I'm not a fan of selecting the default behavior at the soc either. If fact, I would go so far as to not add "default y" - just let the coreboot default be in play unless the mainboard sets its preference.
File src/soc/amd/common/block/pm/pmlib.c:
https://review.coreboot.org/c/coreboot/+/51924/comment/9d4bdc0f_0bf2212b
PS4, Line 10: 0x4
> nit: Use (1 << 2)? It is the same value, but I think it is easier to understand that this is referri […]
amd/common also uses a lot of BIT(x)
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Hello build bot (Jenkins), Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52016
to look at the new patch set (#2).
Change subject: mb/amd/bilby: Enable postcode on port 0x80
......................................................................
mb/amd/bilby: Enable postcode on port 0x80
Only few initial postcodes gets displayed on port 0x80 via LPC bus on
Bilby, removing ESPI as not used in Bilby, to display rest of the
postcodes.
Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
---
M src/mainboard/amd/bilby/Kconfig
M src/mainboard/amd/bilby/early_gpio.c
M src/mainboard/amd/bilby/port_descriptors.c
3 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/52016/2
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Change subject: mb/google/guybrush: add DXIO and DDI descriptors
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/mediatek: add new driver 'msdc' for eMMC
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/common/include/soc/msdc.h:
https://review.coreboot.org/c/coreboot/+/51966/comment/e99830ce_4bf838ca
PS7, Line 6: #include <commonlib/sd_mmc_ctrlr.h>
: #include <commonlib/storage.h>
: #include <commonlib/storage/sd_mmc.h>
: #include <console/console.h>
: #include <device/mmio.h>
: #include <lib.h>
: #include <stdio.h>
: #include <string.h>
Please only include what you need in the header and include the rest in the .c file
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Change subject: vc/amd/fsp/cezanne: update UPD headers
......................................................................
Patch Set 11: Code-Review+2
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