coreboot-gerrit April 2021

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Change in coreboot[master]: mb/amd/bilby: Enable postcode on port 0x80
by Marshall Dawson (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: ritul guru, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52016 ) Change subject: mb/amd/bilby: Enable postcode on port 0x80 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Gerrit-Change-Number: 52016 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 14:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Add custom Wifi SAR for botenflex
by Stanley Wu (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Stanley Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51501 ) Change subject: mb/google/dedede/var/boten: Add custom Wifi SAR for botenflex ...................................................................... Patch Set 5: (4 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/51501/comment/95bda387_392b759f PS4, Line 15: no > Nit: on Done File src/mainboard/google/dedede/variants/boten/variant.c: https://review.coreboot.org/c/coreboot/+/51501/comment/43d68799_48d948f1 PS2, Line 29: NULL > I am making a change to `get_wifi_sar_cbfs_filename()` here: CB:51485 […] Done File src/mainboard/google/dedede/variants/boten/variant.c: https://review.coreboot.org/c/coreboot/+/51501/comment/eaa7ae1a_f353a9d4 PS4, Line 7: #include <ec/google/chromeec/ec.h> > Move it above #include <gpio.h> line. Done https://review.coreboot.org/c/coreboot/+/51501/comment/687c5b4a_03aa7daa PS4, Line 32: 0x90000 > Define a macro for this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f2529a7ad56ff306df98f77cda556656da52a5 Gerrit-Change-Number: 51501 Gerrit-PatchSet: 5 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 14:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set PAM0123 lock
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52165 ) Change subject: soc/intel/xeon_sp: Set PAM0123 lock ...................................................................... soc/intel/xeon_sp: Set PAM0123 lock Set the PAM0123 lock as indicated by the Intel documentation. This is set is finalize to allow any part of coreboot to update the PAM prior to booting. Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/finalize.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h 3 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52165/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 7b16945..7f4a045 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -11,6 +11,7 @@ #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x40 +#define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44 #if !defined(__SIMPLE_DEVICE__) diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index bfcf212..044c1cc 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -4,12 +4,30 @@ #include <console/console.h> #include <console/debug.h> #include <cpu/x86/smm.h> +#include <device/pci.h> +#include <intelpch/lockdown.h> +#include <soc/pci_devs.h> +#include <soc/util.h> + +#include "chip.h" + +static void lock_pam0123(void) +{ + const struct device *dev; + + if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) + return; + + dev = pcidev_path_on_bus(get_stack_busno(1), PCI_DEVFN(SAD_ALL_DEV, SAD_ALL_FUNC)); + pci_or_config32(dev, SAD_ALL_PAM0123_CSR, PAM_LOCK); +} static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); apm_control(APM_CNT_FINALIZE); + lock_pam0123(); post_code(POST_OS_BOOT); } diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 96239ba..01e86e1 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -24,6 +24,7 @@ #define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x40 +#define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44 #if !defined(__SIMPLE_DEVICE__) -- To view, visit https://review.coreboot.org/c/coreboot/+/52165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186 Gerrit-Change-Number: 52165 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Set PCIE secure register lock
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52164 ) Change subject: soc/intel/xeon_sp: Set PCIE secure register lock ...................................................................... soc/intel/xeon_sp: Set PCIE secure register lock Set PCIE SRL as indicated by the Intel documentation. Change-Id: Ifa5bfb2824477b76ba34c3dc0588311f6c320092 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52164/1 diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h index de7a73a..aff336b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h @@ -42,6 +42,12 @@ #define SATAGC 0x9c #define SATAGC_REGLOCK BIT(31) +#define PCH_DEV_SLOT_PCIE 0x1d +#define PCH_DEVFN_PCIE _PCH_DEVFN(PCIE, 0) +#define PCH_DEV_PCIE _PCH_DEV(PCIE, 0) +#define PCIE_MPC 0xd8 +#define SRL BIT(23) + #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 0f032fc..d8c9b6a 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -44,9 +44,16 @@ } } +static void pcie_lockdown_config(int chipset_lockdown) +{ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pci_or_config32(PCH_DEV_PCIE, PCIE_MPC, SRL); +} + void soc_lockdown_config(int chipset_lockdown) { lpc_lockdown_config(chipset_lockdown); pmc_lockdown_config(chipset_lockdown); sata_lockdown_config(chipset_lockdown); + pcie_lockdown_config(chipset_lockdown); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5bfb2824477b76ba34c3dc0588311f6c320092 Gerrit-Change-Number: 52164 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smbus: Lock TCO base
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52163 ) Change subject: soc/intel/common/block/smbus: Lock TCO base ...................................................................... soc/intel/common/block/smbus: Lock TCO base Lock the TCO base when locking the TCO settings as indicated by the Intel documentation. Change-Id: Ifdeae9c65e6694a36c9d1d609904a1daf181bdb1 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/52163/1 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 8ec24b6..0ac7d1a 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -22,6 +22,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK BIT(0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -49,12 +50,16 @@ void tco_lockdown(void) { - uint16_t tcocnt; + uint16_t reg; /* TCO Lock down */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; - tco_write_reg(TCO1_CNT, tcocnt); + reg = tco_read_reg(TCO1_CNT); + reg |= TCO_LOCK; + tco_write_reg(TCO1_CNT, reg); + + reg = tco_read_reg(TCOCTL); + reg |= TCO_BASE_LOCK; + tco_write_reg(TCOCTL, reg); } uint32_t tco_reset_status(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/52163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdeae9c65e6694a36c9d1d609904a1daf181bdb1 Gerrit-Change-Number: 52163 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Set SATA REGLOCKs
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Patrick Rudolph. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52162 ) Change subject: soc/intel/xeon_sp: Set SATA REGLOCKs ...................................................................... soc/intel/xeon_sp: Set SATA REGLOCKs Set the SATA and SSATA REGLOCK as indicated by the Intel documentation. Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/52162/1 diff --git a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h index 41ec7e1..de7a73a 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h +++ b/src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h @@ -13,6 +13,10 @@ /* PCH Device info */ +#define PCH_DEV_SLOT_MROM0 0x11 +#define PCH_DEVFN_SSATA _PCH_DEVFN(MROM0, 5) +#define PCH_DEV_SSATA _PCH_DEV(MROM0, 5) + #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 #define XHCI_FUNC_NUM 0x0 @@ -32,6 +36,12 @@ #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) +#define SATAGC 0x9c +#define SATAGC_REGLOCK BIT(31) + #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 3a12110..0f032fc 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> +#include <device/pci.h> #include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> +#include <soc/pci_devs.h> #include <soc/pm.h> static void lpc_lockdown_config(int chipset_lockdown) @@ -29,13 +31,22 @@ /* Make sure payload/OS can't trigger global reset */ pmc_global_reset_disable_and_lock(); + + /* Lock PMC stretch policy */ + pci_or_config32(PCH_DEV_PMC, GEN_PMCON_B, SLP_STR_POL_LOCK); +} + +static void sata_lockdown_config(int chipset_lockdown) +{ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + pci_or_config32(PCH_DEV_SATA, SATAGC, SATAGC_REGLOCK); + pci_or_config32(PCH_DEV_SSATA, SATAGC, SATAGC_REGLOCK); + } } void soc_lockdown_config(int chipset_lockdown) { - /* LPC lock down configuration */ lpc_lockdown_config(chipset_lockdown); - - /* PMC lock down configuration */ pmc_lockdown_config(chipset_lockdown); + sata_lockdown_config(chipset_lockdown); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b Gerrit-Change-Number: 52162 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/ocp/deltalake: Add SATA device to device tree
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang. Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52161 ) Change subject: mainboard/ocp/deltalake: Add SATA device to device tree ...................................................................... mainboard/ocp/deltalake: Add SATA device to device tree Add the SATA device to the device tree so it may be found when trying to write SATA registers. Otherwise, it fails on "requests hidden 00:17.0 PCI: dev is NULL!" Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/52161/1 diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 08ac3e3..e6f53be 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -86,6 +86,7 @@ device pci 16.0 on end # Communication controller: Intel Device a23a device pci 16.1 on end # Communication controller: Intel Device a23b device pci 16.4 on end # Communication controller: Intel Device a23e + device pci 17.0 on end # Intel C620 Series Chipset Family SATA Controller [AHCI mode] device pci 1c.0 on end # PCI bridge: Intel Device a210 device pci 1c.4 on end # PCI bridge: Intel Device a214 device pci 1c.5 on end # PCI bridge: Intel Device a215 -- To view, visit https://review.coreboot.org/c/coreboot/+/52161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6 Gerrit-Change-Number: 52161 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Set MSR locks
by Marc Jones (Code Review) 07 Apr '21

07 Apr '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52160 ) Change subject: soc/intel/xeon_sp: Set MSR locks ...................................................................... soc/intel/xeon_sp: Set MSR locks Set MSR locks as indicated by the Intel documents. The following MSRs settings are locked: MSR_FEATURE_CONFIG AES enable/disable lock TURBO_ACTIVATION_RATIO_LOCK This also adds PARALLEL_MP_AP_WORK to enable running on APs to set each CPU MSR. Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/msr.h 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52160/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 61ab750..050511a 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,6 +36,7 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP + select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 500f83e..34e0e27 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <console/debug.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> #include <device/pci.h> #include <intelblocks/acpi.h> #include <intelblocks/gpio.h> @@ -12,6 +13,7 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/cpu.h> +#include <soc/msr.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/p2sb.h> @@ -141,6 +143,22 @@ } +static void set_msr_locks(void *unused) +{ + /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */ + msr_t msr; + + /* Lock Turbo */ + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); + + /* Lock AES enable */ + msr = rdmsr(MSR_FEATURE_CONFIG); + msr.lo |= FEATURE_CONFIG_LOCK; + wrmsr(MSR_FEATURE_CONFIG, msr); +} + static void chip_final(void *data) { /* Lock SBI */ @@ -157,6 +175,7 @@ uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); p2sb_hide(); diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index dd05adc..3d68bf2 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -5,6 +5,9 @@ #include <intelblocks/msr.h> +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_LOCK BIT(0) + #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Gerrit-Change-Number: 52160 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by Marshall Dawson (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: ritul guru, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51674 ) Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... Patch Set 7: (2 comments) File src/mainboard/amd/bilby/early_gpio.c: https://review.coreboot.org/c/coreboot/+/51674/comment/dbc1b780_a5ed9967 PS7, Line 22: nit: remove this extra whitespace here File src/mainboard/amd/bilby/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/51674/comment/4fad51a8_c786dcca PS7, Line 73: const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) I would leave lines 72 and 73 as-is and put the tabs back in. This looks odd having the statements below aligned with the functions arguments. -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 7 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 14:13:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards
by Aaron Durbin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Aseda Aboagye, Karthik Ramasubramanian. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards ...................................................................... Patch Set 1: (1 comment) This change is ready for review. File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/52147/comment/37f51d3a_ab810b0c PS1, Line 38: HECI_DISABLE_USING_SMM > Should we drop this for entire dedede family i.e. […] An argument can be made for keeping things the way they were as well as consistency everywhere. Karthik, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 14:11:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2021