coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM...
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Frans Hendriks, Patrick Rudolph, Wim Vervoorn. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 ) Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > I noticed your concern in raminit_common(). > Should disable_save_data be set in soc_pre_ram_init when VBOOT_STARTS_IN_ROMSTAGE? > No. > Any suggestions for better solution? Try https://review.coreboot.org/c/coreboot/+/52157 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 13:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Frans Hendriks. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52157 ) Change subject: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: untested -- To view, visit https://review.coreboot.org/c/coreboot/+/52157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Gerrit-Change-Number: 52157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 13:31:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52157 ) Change subject: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE ...................................................................... drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE This guards code accessing the vboot context which does not exist if vboot starts after romstage. Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/52157/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 8b26ea5..f97031d 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -285,7 +285,8 @@ * In recovery mode, force retraining if the memory retrain * switch is set. */ - if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch()) + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && vboot_recovery_mode_enabled() + && get_recovery_mode_retrain_switch()) return -1; cr = lookup_region(&region, type); -- To view, visit https://review.coreboot.org/c/coreboot/+/52157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Gerrit-Change-Number: 52157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM...
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 ) Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > The MRC cache should not call vboot methods in romstage, but it should still be possible to use MRC […] I noticed your concern in raminit_common(). Should disable_save_data be set in soc_pre_ram_init when VBOOT_STARTS_IN_ROMSTAGE? Any suggestions for better solution? -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 13:19:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Hung-Te Lin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Angel Pons, Wenbin Mei, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 6: (28 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51966/comment/ba4ae302_849bd7ad PS2, Line 7: mmc: Add MTK mmc driver support > Done Ack File src/mainboard/google/asurada/mainboard.c: https://review.coreboot.org/c/coreboot/+/51966/comment/43687879_c30e8457 PS1, Line 233: struct msdc_ctrlr msdc_host; > Ack Ack https://review.coreboot.org/c/coreboot/+/51966/comment/47f3e0bd_105c101e PS1, Line 243: (void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE > Done Ack https://review.coreboot.org/c/coreboot/+/51966/comment/5b4e2a96_e72d6d39 PS1, Line 247: 400*1000 > Yes, 400KHz is init clock, and all eMMCs will support it. Ack File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/0f562ebf_60e0b6d2 PS6, Line 97: SDC_CMD_DTYPE_S And if you use bit fields... DEFINE_BITFIELD(SDC_CMD_DTYPE, 12, 11) DEFINE_BIT(SDC_CMD_WD, 13) DEFINE_BIT(SDC_CMD_STOP, 14) DEFINE_BITFIELD(SDC_CMD_BLK_LEN, 27, 16) DEFINE_BITFIELD(SDC_CMD_CMD, 5, 0) The numbers should align to the datasheet bit definition. However, I also saw how these macros were used in prepare_cmd, so it's probably fine to keep how you implement them today. https://review.coreboot.org/c/coreboot/+/51966/comment/0fc9f196_63a90fdb PS6, Line 142: 5*100 5 * 100 https://review.coreboot.org/c/coreboot/+/51966/comment/61ace8f3_a835748f PS6, Line 143: 1000*1000 1000 * 1000 File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/66e24d56_90219283 PS5, Line 25: > Please avoid mixing tabs and spaces to align the values. […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/e0992a87_3d4ae9dc PS5, Line 62: /*--------------------------------------------------------------------------*/ : /* Register Mask */ : /*--------------------------------------------------------------------------*/ > will you consider redefining all the masks, using DEFINE_BITFIELDS ? Ack https://review.coreboot.org/c/coreboot/+/51966/comment/98e1d1e9_20a2358c PS5, Line 102: #define SDC_CMD_CMD_S 0 > If I understand correctly, the `_S` suffix means shift, and the `_M` suffix means mask. […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/1feb3b23_ba0574b8 PS5, Line 167: int > nit: bool? Ack File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/28b9a777_d165063a PS2, Line 70: udelay(1); > Ack Ack https://review.coreboot.org/c/coreboot/+/51966/comment/118a50e7_9a760c85 PS2, Line 72: MSDC_NOT_READY > Done Ack https://review.coreboot.org/c/coreboot/+/51966/comment/d99e8640_54fc1848 PS2, Line 349: host > We need "msdc_ctrlr *" pointer as first parameter for the "msdc_start_command" function, so it shoul […] I think it's a pretty bad idea to recast (struct sd_mmc_ctrlr *) to (struct msdc_ctrlr *). That's simply making the implementation pretty confusing. Yes I know sdhci.c is doing this but let's try not making more bad examples. Can you replace these with container_of macro? Take a look at src/soc/ti/am335x/mmc.c to see how this can be properly done without casting. https://review.coreboot.org/c/coreboot/+/51966/comment/ca877dd4_1172ebf0 PS2, Line 385: clrsetbits_le32 > Yes Ack File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/ec840ebb_ac9a4319 PS5, Line 12: int > unsigned int Ack https://review.coreboot.org/c/coreboot/+/51966/comment/4df83794_ac42194b PS5, Line 14: static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; } > There's a DIV_ROUND_UP macro in commonlib/bsd/helpers. […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/e90ee246_8a425669 PS5, Line 22: write32(reg, tv); > This could be replaced with: […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/71cad540_616c786a PS5, Line 33: int > u32? Ack https://review.coreboot.org/c/coreboot/+/51966/comment/0595b4df_d9ca934e PS5, Line 45: return MSDC_SUCCESS; > Also see the wait_us() macro. Ack https://review.coreboot.org/c/coreboot/+/51966/comment/7077d4f5_73d27aa2 PS5, Line 57: while (!(reg & mask)) { > nit: I would use a do-while loop like on `msdc_poll_timeout` Ack https://review.coreboot.org/c/coreboot/+/51966/comment/89fd6504_68376efd PS5, Line 61: *status = reg; > Missing a null pointer check? […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/14368656_fc61fdda PS5, Line 162: resp = 0x1; > nit: you could return the value directly Ack https://review.coreboot.org/c/coreboot/+/51966/comment/1240323b_b6379787 PS5, Line 243: ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M); > I'd suggest splitting this in multiple statements: […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/b9192bd0_4ee4018a PS5, Line 328: return cmd_ret; > nit: Just return `msdc_start_command(host, cmd, data)` directly? Ack https://review.coreboot.org/c/coreboot/+/51966/comment/cb42cc71_08379c24 PS5, Line 454: sizeof(int) > nit: sizeof(status) ? Ack https://review.coreboot.org/c/coreboot/+/51966/comment/4efc1bcb_74a0001e PS5, Line 477: memset(&media, 0, sizeof(media)); > You can zero-initialize media without memset: […] Ack File src/soc/mediatek/mt8192/Makefile.inc: https://review.coreboot.org/c/coreboot/+/51966/comment/038b2897_eddfe5b0 PS5, Line 55: ramstage-y += ../common/msdc.c > this change should go to next patch, when you modify 8192 config to add msdc. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 6 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 13:03:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/mb/ocp: Update Delta Lake documentation
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Stefan Reinauer, Angel Pons, ron minnich, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51824 ) Change subject: Documentation/mb/ocp: Update Delta Lake documentation ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf Gerrit-Change-Number: 51824 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 12:58:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/mb/ocp: Update Delta Lake documentation
by Sumeet R Pawnikar (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Stefan Reinauer, Angel Pons, ron minnich, Tim Chu. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51824 ) Change subject: Documentation/mb/ocp: Update Delta Lake documentation ...................................................................... Patch Set 7: (1 comment) File Documentation/mainboard/ocp/deltalake.md: https://review.coreboot.org/c/coreboot/+/51824/comment/772a4b6d_94cf3827 PS7, Line 66: other coreboot Does this header file still contain DeltaLake VPDs ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf Gerrit-Change-Number: 51824 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 12:46:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: select mmc storage config
by Hung-Te Lin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Xi Chen, Martin Roth, Paul Menzel, Wenbin Mei. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52014 ) Change subject: mb/google/asurada: select mmc storage config ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52014/comment/7ad58922_0cdbbdb8 PS4, Line 11: This adds -100 ms to the boot. I think this is not true; 100ms is saved when early-mmc is called, so in this change (no early_mmc) I think it should not save 100ms. Probably no boot time difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/52014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Gerrit-Change-Number: 52014 Gerrit-PatchSet: 4 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 12:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM...
by Arthur Heymans (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Frans Hendriks, Patrick Rudolph, Wim Vervoorn. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 ) Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... Patch Set 7: Code-Review-2 (1 comment) Patchset: PS7: The MRC cache should not call vboot methods in romstage, but it should still be possible to use MRC cache with VBOOT. I suspect this breaks S3 resume. -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 12:07:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: select mmc storage config
by Wenbin Mei (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Martin Roth, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52014 to look at the new patch set (#4). Change subject: mb/google/asurada: select mmc storage config ...................................................................... mb/google/asurada: select mmc storage config Select mmc storage config for asurada. Build MTK host mmc driver. This adds -100 ms to the boot. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b --- M src/mainboard/google/asurada/Kconfig M src/soc/mediatek/mt8192/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/52014/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Gerrit-Change-Number: 52014 Gerrit-PatchSet: 4 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021