coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: 3rdparty/blobs: Update blobs pointer to f388b6794e6f
by Patrick Georgi (Code Review) 07 Apr '21

07 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52112 ) Change subject: 3rdparty/blobs: Update blobs pointer to f388b6794e6f ...................................................................... 3rdparty/blobs: Update blobs pointer to f388b6794e6f mb/google/guybrush: Update APCB - disable debug mb/google/guybrush: Add APCB to get through memory training soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode soc/mediatek/mt8192: Update MCUPM firmware soc/mediatek/mt8192: Add version info for SSPM TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I445d753c712670fe80efcdf29459736df2b76666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/3rdparty/blobs b/3rdparty/blobs index fc2d4e2..f388b67 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit fc2d4e2587e1260f4fe4114e797541229bcc6b9e +Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 -- To view, visit https://review.coreboot.org/c/coreboot/+/52112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445d753c712670fe80efcdf29459736df2b76666 Gerrit-Change-Number: 52112 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))
by Patrick Georgi (Code Review) 07 Apr '21

07 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52111 ) Change subject: util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET)) ...................................................................... util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET)) This change was promised as a follow-up in change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52111 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/bincfg/Makefile 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 2dc5073..ca375a5 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -20,21 +20,21 @@ # Use this target to generate GbE for X200 gen-gbe-ich9m: $(TARGET) - ./bincfg gbe-ich9m.spec gbe-ich9m.set gbe1.bin + $(abspath $(TARGET)) gbe-ich9m.spec gbe-ich9m.set gbe1.bin # duplicate binary as per spec cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin # Use this target to generate GbE for X220/x230 gen-gbe-82579LM: $(TARGET) - ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + $(abspath $(TARGET)) gbe-82579LM.spec gbe-82579LM.set gbe1.bin # duplicate binary as per spec cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin # Use this target to generate IFD for X200 gen-ifd-x200: $(TARGET) - ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin + $(abspath $(TARGET)) ifd-x200.spec ifd-x200.set flashregion_0_fd.bin clean: rm -f *.lex.c *.tab.c *.tab.h *.o bincfg flashregion_0_fd.bin flashregion_3_gbe.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/52111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Gerrit-Change-Number: 52111 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP
by Frank Wu (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Martin Roth, Kangheui Won, Paul Menzel, EricR Lai. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52127 ) Change subject: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi Google, Would you help to review the CL? The new ACPI name in coreboot and kernel can work fine. The result is positive in b/177971830#comment185. -- To view, visit https://review.coreboot.org/c/coreboot/+/52127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Gerrit-Change-Number: 52127 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 08:44:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/lindar: Configure unused GPIOs as NC
by Kevin Chang (Code Review) 07 Apr '21

07 Apr '21

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52151 ) Change subject: mb/google/volteer/var/lindar: Configure unused GPIOs as NC ...................................................................... mb/google/volteer/var/lindar: Configure unused GPIOs as NC Configure unused GPIOs as NC BUG=b:180830117 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 --- M src/mainboard/google/volteer/variants/lindar/gpio.c 1 file changed, 26 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/52151/1 diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 44e3148..a38f7d7 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -14,6 +14,8 @@ PAD_CFG_GPO(GPP_A10, 1, DEEP), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ @@ -30,8 +32,6 @@ /* B22 : GSPI1_MOSI ==> NOT USED */ PAD_NC(GPP_B22, NONE), - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C10 : UART0_RTS# ==> USI_RST_L */ PAD_CFG_GPO(GPP_C10, 0, DEEP), /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ @@ -52,10 +52,10 @@ /* D17 : ISH_GP4 ==> EN_CVF_PWR */ PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ @@ -64,16 +64,38 @@ PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E21, NONE), /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> NC */ + PAD_NC(GPP_F22, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), /* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */ @@ -133,8 +155,6 @@ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C0 : SMBCLK ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), -- To view, visit https://review.coreboot.org/c/coreboot/+/52151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 Gerrit-Change-Number: 52151 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52027 ) Change subject: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry ...................................................................... mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry Following commit de50d39, remove the `volume` entry from cmos.default. Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Signed-off-by: Nicola Corna <nicola(a)corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52027 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/sapphire/pureplatinumh61/cmos.default 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.default b/src/mainboard/sapphire/pureplatinumh61/cmos.default index 579945d..7cd30cc 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.default +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.default @@ -2,6 +2,5 @@ debug_level=Debug power_on_after_fail=Enable nmi=Enable -volume=0x3 sata_mode=AHCI hyper_threading=Enable -- To view, visit https://review.coreboot.org/c/coreboot/+/52027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Gerrit-Change-Number: 52027 Gerrit-PatchSet: 3 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Arthur Heymans, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 ) Change subject: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52128/comment/a11f01cc_57bdd893 PS2, Line 9: ASSERTION ERROR > > ASSERTION ERROR: file 'src/security/vboot/common.c', line 23 […] Done Patchset: PS4: > The proper fix would be to have the VBOOT related part of the MRC cache driver depend on !VBOOT_STAR […] Will check. -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 08:21:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Frans Hendriks, Wim Vervoorn. Hello build bot (Jenkins), Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52128 to look at the new patch set (#5). Change subject: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data ...................................................................... mb/faceboot/fbg1701/romstage.c: Set disable_saved_data ASSERTION ERROR: file 'src/security/vboot/common.c', line 23 occurs when reading RW_MRC_CACHE if VBOOT is enabled. MRC cache is loaded in early stage of ROMSTAGE. There is not enough CAR space available for vboot workbuffer. CBMEM can not be used since memory init is not executed. When VBOOT is enabled, disable_saved_data is set disabling loading MRC data. BUG = N/A TEST = Build and boot facebook FBG1701 with VBOOT enabled and disabled. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 --- M src/mainboard/facebook/fbg1701/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52128/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: enable SOL console via Kconfig
by Michael Niewöhner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Tim Wawrzynczak, Morgan Jang. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52091 ) Change subject: mb/ocp/deltalake: enable SOL console via Kconfig ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > On my Delta Lake SOL does not work with this change. Thanks for testing! Will have a look again -- To view, visit https://review.coreboot.org/c/coreboot/+/52091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Gerrit-Change-Number: 52091 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 08:13:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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Change in coreboot[master]: tests/lib/malloc-test: Fix possible memory overrun
by Jakub Czapiga (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Paul Menzel, Julius Werner. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52136 ) Change subject: tests/lib/malloc-test: Fix possible memory overrun ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Sorry, where is the overrun here? These two symbols point to the same address, right? […] Yes, _heap points to the beginning of _test_heap. Pointers should be equal. This Coverity report looked suspicious to me. It's not strange that Coverity does not know how to parse TEST_SYMBOL() macros and get correct buffer from symbol. Should I create changes like that in future but with comment like: "To silence Coverity", or just ignore irrelevant "bugs" reported by it? (Should I abandon this change as well?) -- To view, visit https://review.coreboot.org/c/coreboot/+/52136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19f0718c657d565e515157e66367573e08f51254 Gerrit-Change-Number: 52136 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 07:26:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lillupup: provide additional VBT for lillipup OLED sku
by Kevin Chang (Code Review) 07 Apr '21

07 Apr '21

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52150 ) Change subject: lillupup: provide additional VBT for lillipup OLED sku ...................................................................... lillupup: provide additional VBT for lillipup OLED sku Lillipup add two sku for OLED panel. Additional VBT is necessary to modify PWM source from VESA eDP AUX interface BUG=b:183630802 TEST=emerge-volteer coreboot-private-files-baseboard-volteer check vbt_lillipup.bin is under build folder and check in CPU log. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 --- A src/mainboard/google/volteer/variants/lindar/include/variant/sku.h M src/mainboard/google/volteer/variants/lindar/variant.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/52150/1 diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/sku.h b/src/mainboard/google/volteer/variants/lindar/include/variant/sku.h new file mode 100644 index 0000000..83f98c8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/sku.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +enum { + SKU_6_OLED = 0x80006, + SKU_7_OLED = 0x80007, +}; + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/volteer/variants/lindar/variant.c b/src/mainboard/google/volteer/variants/lindar/variant.c index 2d10dc6..24ad708 100644 --- a/src/mainboard/google/volteer/variants/lindar/variant.c +++ b/src/mainboard/google/volteer/variants/lindar/variant.c @@ -2,6 +2,9 @@ #include <fw_config.h> #include <sar.h> +#include <ec/google/chromeec/ec.h> +#include <drivers/intel/gma/opregion.h> +#include <variant/sku.h> const char *get_wifi_sar_cbfs_filename(void) { @@ -12,3 +15,18 @@ return WIFI_SAR_CBFS_DEFAULT_FILENAME; } + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id; + + sku_id = google_chromeec_get_board_sku(); + + switch (sku_id) { + case SKU_6_OLED: + case SKU_7_OLED: + return "vbt-lillipup.bin"; + default: + return "vbt.bin"; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Gerrit-Change-Number: 52150 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021