coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU
by John Zhao (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Li1 Feng, John Zhao. Hello build bot (Jenkins), Li1 Feng, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52137 to look at the new patch set (#5). Change subject: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU ...................................................................... mb/google/volteer: Add EC_HOST_EVENT_PD_MCU This change adds the EC_HOST_EVENT_PD_MCU to be dark resume source. BUG=b:183140386 TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC synchronized. AP got port partner disconnection. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I44e4075f42e9a95d26fe766489630dac0bc61b05 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/52137/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44e4075f42e9a95d26fe766489630dac0bc61b05 Gerrit-Change-Number: 52137 Gerrit-PatchSet: 5 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: timestamp: Add helper fucntions
by Julius Werner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Aaron Durbin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/a9d7a87a_75c3518c PS3, Line 7: Add helper fucntions > Actually replace ts[X] with time_stamp_X. Sorry, I used the wrong name from the follow-up CL. I think the time_from_base in your naming is confusing, because all timestamp_add()s are relative to the base. The real difference in the one you propose is just that you're using a different scale (microseconds instead of TSC ticks). I still think this might all be easier if we first change the timestamp library to do everything in microseconds. Then you just need a timestamp_rewind_base(0 - ts[3]) with one argument, and then you can timestamp_add() all the other ones directly (which are already in microseconds to the same new base). File src/include/timestamp.h: https://review.coreboot.org/c/coreboot/+/51445/comment/cf36defb_7fb72d93 PS3, Line 26: * Add a new raw timestamp in microseconds into timestamp_table at index 'n'. > IIUC, the reason why x86 platforms store in TSC frequency is because the timestamp values are basica […] Yeah I know, but that's one division instruction, it shouldn't really be noticeable. That's the same thing that happens any time you call a stopwatch function, and all the Arm platforms do that too. I feel like we're getting so far into the woods with all these frequencies (especially with all the new APIs you're proposing) that it would really be a lot easier to just force everything to be in microseconds. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 00:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: include/assert.h: Use mock_assert() for ENV_TEST targets
by Julius Werner (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51804 ) Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets ...................................................................... Patch Set 3: (4 comments) File src/include/assert.h: https://review.coreboot.org/c/coreboot/+/51804/comment/5ee126c2_322ffb73 PS3, Line 12: const char *const file, const int line); nit: maybe declare this right next to MOCK_ASSERT() so it's more obvious where it belongs to? https://review.coreboot.org/c/coreboot/+/51804/comment/b14dc855_5a014079 PS3, Line 38: mock_assert((result), (expression), (file), (line)) You can just use __ASSERT_FILE__ and __ASSERT_LINE__ in here, no need to pass so many things. https://review.coreboot.org/c/coreboot/+/51804/comment/2d4854ab_65b5edf1 PS3, Line 71: MOCK_ASSERT(0, "BUG ENCOUNTERED", \ Bad indentation. File src/include/assert.h: https://review.coreboot.org/c/coreboot/+/51804/comment/32f4963a_525afcf7 PS1, Line 67: #define assert(statement) mock_assert(statement, #statement, __FILE__, __LINE__) > ASSERT(), ASSERT_MSG() and BUG() have different input parameters. […] I mean you could do something like #define HANDLE_ASSERT(reason, message) do { if (ENV_TEST) mock_assert(result, message, __ASSERT_FILE__, __ASSERT_LINE__); if (CONFIG(FATAL_ASSERTS)) hlt(); to deduplicate things a bit more. But I'm fine with what you have right now as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/51804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Gerrit-Change-Number: 51804 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 00:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
by Julius Werner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Martin Roth, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51838 ) Change subject: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > There's compiler tooling for that since gcc6 (-Wmisleading-indentation) and while it's also just heu […] If it does the same job just as well, I'm happy with that solution too. (If it existed since GCC 6 why haven't we had this turned on for years?) -- To view, visit https://review.coreboot.org/c/coreboot/+/51838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f Gerrit-Change-Number: 51838 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:54:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: tests/lib/malloc-test: Fix possible memory overrun
by Julius Werner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jakub Czapiga, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52136 ) Change subject: tests/lib/malloc-test: Fix possible memory overrun ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Sorry, where is the overrun here? These two symbols point to the same address, right? Please always try to make a clear distinction between actual bugs and false positives from Coverity and don't just blindly do what the program tells you. (I'm okay with this change to silence the warning if you want it, but commit messages should make clear when something is an actual bug and when it's just placating an overzealous tool.) -- To view, visit https://review.coreboot.org/c/coreboot/+/52136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19f0718c657d565e515157e66367573e08f51254 Gerrit-Change-Number: 52136 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:52:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Update CpuRatio settings
by Karthik Ramasubramanian (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Kaiyen Chang, Angel Pons, Patrick Rudolph. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52029 ) Change subject: soc/intel/jasperlake: Update CpuRatio settings ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Why is this issue/system reset observed only on certain devices instead of all? Is the cpu ratio configuration by FSP persistent across system resets, so that FSP does get stuck in reset loop? -- To view, visit https://review.coreboot.org/c/coreboot/+/52029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5 Gerrit-Change-Number: 52029 Gerrit-PatchSet: 4 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Evan Green <evgreen(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:28:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/tigerlake: Add Acoustic features
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50870 ) Change subject: intel/tigerlake: Add Acoustic features ...................................................................... intel/tigerlake: Add Acoustic features On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 8 files changed, 15 insertions(+), 70 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5f05844..58d1aac 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -352,6 +352,11 @@ .vnn_sx_voltage_mv = 1250, }" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + device domain 0 on device ref igpu on end device ref dptf on diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index c111731..1549aaf 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -57,17 +57,6 @@ }" register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" - # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index a29ce1c..87c1417 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -2,17 +2,6 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 10e199a..bce953b 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -49,17 +49,6 @@ register "HybridStorageMode" = "1" - # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - device domain 0 on device ref ipu on end device ref i2c0 on diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index f517de2..635a310 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -65,17 +65,6 @@ register "HybridStorageMode" = "1" - # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - device domain 0 on device ref dptf on chip drivers/intel/dptf diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index c1002ef..a1453f9 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -19,17 +19,6 @@ # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" - # Acoustic settings - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" - register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" - register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - device domain 0 on device ref dptf on chip drivers/intel/dptf diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index af9b310..1a1ba73 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -186,22 +186,21 @@ /* * Offset 0x054B - Disable Fast Slew Rate for Deep Package - * C States for VR domains. Disable Fast Slew Rate for Deep - * Package C States based on Acoustic Noise Mitigation feature - * enabled. The domains are IA,GT,SA,VLCC and FIVR. + * C States for VCCin in VR domain. Disable Fast Slew Rate + * for Deep Package C States based on Acoustic Noise + * Mitigation feature enabled. * 0 - False * 1 - True */ - uint8_t FastPkgCRampDisable[VR_DOMAIN_MAX]; + uint8_t FastPkgCRampDisable; /* * Offset 0x0550 - Slew Rate configuration for Deep Package - * C States for VR domains. Slew Rate configuration for Deep - * Package C States for VR domains based on Acoustic Noise - * Mitigation feature enabled. The domains are IA,GT,SA,VLCC and FIVR. - * Slew rates are defined as enum slew_rate. + * C States for VCCin in VR domain. Slew Rate configuration + * for Deep Package C States for VR domain based on Acoustic + * Noise Mitigation feature enabled. */ - uint8_t SlowSlewRate[VR_DOMAIN_MAX]; + uint8_t SlowSlewRate; /* SATA related */ uint8_t SataEnable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 6bd4a7c..9fbf9bd 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -332,12 +332,8 @@ } params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; - memcpy(&params->SlowSlewRate, &config->SlowSlewRate, - ARRAY_SIZE(config->SlowSlewRate) * sizeof(config->SlowSlewRate[0])); - - memcpy(&params->FastPkgCRampDisable, &config->FastPkgCRampDisable, - ARRAY_SIZE(config->FastPkgCRampDisable) * - sizeof(config->FastPkgCRampDisable[0])); + params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; + params->SlowSlewRate[0] = config->SlowSlewRate; /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/50870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Gerrit-Change-Number: 50870 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/tigerlake: Add Acoustic features
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Shaunak Saha, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50870 ) Change subject: intel/tigerlake: Add Acoustic features ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50870/comment/8b3e0985_8166bafa PS2, Line 9: Expose the following FSP UPD interface into coreboot: : - AcousticNoiseMitigation : - FastPkgCRampDisable : - SlowSlewRateFo > Will fix. Done File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/50870/comment/f2f53202_343ace8d PS2, Line 187: VR domain > Will Fix Done https://review.coreboot.org/c/coreboot/+/50870/comment/10993339_0a6dfa5a PS2, Line 193: FastPkgCRampDisable > Correct. Done https://review.coreboot.org/c/coreboot/+/50870/comment/f81f300f_43731379 PS2, Line 197: VR domain > Will Fix. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Gerrit-Change-Number: 50870 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Set Power state after power failure
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52049 ) Change subject: soc/amd/cezanne: Set Power state after power failure ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Gerrit-Change-Number: 52049 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:24:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Furquan Shaikh (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 ) Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... Patch Set 4: Code-Review+2 (2 comments) File src/soc/amd/common/block/pm/Kconfig: https://review.coreboot.org/c/coreboot/+/51924/comment/83e50872_d0a52568 PS4, Line 5: select POWER_STATE_DEFAULT_ON_AFTER_FAILURE nit: Probably add it as: ``` config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y ``` so that mainboard can override it if required. (Reference: CB:43338) File src/soc/amd/common/block/pm/pmlib.c: https://review.coreboot.org/c/coreboot/+/51924/comment/802866c8_e9ef69cc PS4, Line 10: 0x4 nit: Use (1 << 2)? It is the same value, but I think it is easier to understand that this is referring to bit 2. -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 23:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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