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Change subject: soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
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Patch Set 2: Code-Review+2
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Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/e3e62ae2_8ee375de
PS1, Line 54: HIGH
> Just for my own knowledge, what's the correct way to handle these timings constraints? The i2c ACPI […]
Since FSP/AGESA is the one that is configuring the PCIE root ports, these timing constraints need to be handled in coreboot (bootblock or romstage). It actually depends on the hardware design as well. If there are no separate power enables for a device e.g. if PP3300_NVME is driven high by S0 rail, then all we need to do for SSD_AUX_RESET_L is ensure it gets deasserted 'x' ms from S0 rail going high. However, if there is a power enable which is under software control, then we need more logic for meeting the timing constraints. One way to handle this is adding enable GPIO control in bootblock and reset deassertion in romstage. Or adding explicit calls to mdelay() if more delay is required.
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Change subject: ec/lenovo/h8/acpi: fix wrong calculation
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52144/comment/9de5d2af_870700a2
PS2, Line 8:
It’d be great, if you elaborated a bit.
https://review.coreboot.org/c/coreboot/+/52144/comment/6a37189d_65019f75
PS2, Line 9: Fixes: commit 81d55cf6d62ac710df030fc02dd3ca00f3d80405
Please use the common style referencing the commit (also known from the Linux kernel).
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Change subject: lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Let's get this in, but I think we should also move these things out of vendorcode (after which we co […]
Where would you move them to? Coding style is not the only thing that sets vendorcode apart... for example, the Eltan stuff is following coreboot's coding style and was written specifically for coreboot (so I think it can benefit from checkpatch), but it's also implementing something that we specifically said we didn't want in coreboot proper (because it's solving the same problems that the core vboot and measured boot libraries basically already solve, and we don't want to maintain tons of different incompatible implementations for the same purpose). vendorcode is sort of a compromise for when vendors want to just quickly throw in their own stuff to support what they need without going through the full review process.
I think it's fine if you want to more officially separate the stuff that follows coreboot code style from the stuff that doesn't, but I think there's still a need for "vendorcode" that's not the same as normal coreboot code in the latter category.
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Change subject: mb/google/guybrush: Unmask eSPI keyboard IRQ
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File src/mainboard/google/guybrush/mainboard.c:
https://review.coreboot.org/c/coreboot/+/52143/comment/9013a4ce_763dd9c1
PS3, Line 119: pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
> Files b/184678786 so we can work out the API change. Also added a TODO to the code.
Thanks Raul!
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Change subject: [WIP] mb/google/guybrush/port_descriptors: add dummy descriptors
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
This fixes graphics so we no longer need an OS workaround.
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Change subject: mb/google/guybrush: Unmask eSPI keyboard IRQ
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS3:
> +1. We already have vw_irq_polarity. […]
Ack
File src/mainboard/google/guybrush/mainboard.c:
https://review.coreboot.org/c/coreboot/+/52143/comment/8d03b424_311d5cc9
PS3, Line 119: pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
> I think this should be done as part of `espi_configure()`. […]
Files b/184678786 so we can work out the API change. Also added a TODO to the code.
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Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52143
to look at the new patch set (#4).
Change subject: mb/google/guybrush: Unmask eSPI keyboard IRQ
......................................................................
mb/google/guybrush: Unmask eSPI keyboard IRQ
PS/2 keyboard used IRQ 1.
BUG=none
TEST=Boot guybrush and see internal keyboard working
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1
---
M src/mainboard/google/guybrush/mainboard.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/52143/4
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