coreboot-gerrit April 2021

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Change in coreboot[master]: timestamp: Add helper fucntions
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Julius Werner, Angel Pons, Subrata Banik, Aaron Durbin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/43695f91_1c1bf362 PS3, Line 7: Add helper fucntions > I think the time_from_base in your naming is confusing, because all timestamp_add()s are relative to the base. `timestamp_add()` actually takes an absolute time and then converts it into a value relative to the base(https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/mast…: ``` ts_time -= ts_table->base_time; ``` I mentioned it as `time_from_base` because it is the delta from the base rather than an absolute time. See https://imgur.com/7wWcBbv (I have never really shared snapshots here before, so if there is another preferred way, please let me know). Yes, it is possible to do the math at the caller site to perform tX + (b' - t4) and then use timestamp_add to subtract (b' - t4), but I think that is unnecessary. With that we can avoid such calculations and comments to convert entries back and forth between relative and absolute times: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…. > The real difference in the one you propose is just that you're using a different scale (microseconds instead of TSC ticks). I did sneak in the scale parameter in the same function to allow the caller to provide the conversion factor. In this case, one time is in mseconds and other in TSC. But even if we move everything to microseconds, I think we are still going to require the same functions i.e. rewind_from_base() and timestamp_add_time_from_base() as commented above. So, there is more difference that just a different scale. > I still think this might all be easier if we first change the timestamp library to do everything in microseconds. I agree that changing to microseconds can make things slightly simpler, but it isn't going to eliminate the functions mentioned above. File src/include/timestamp.h: https://review.coreboot.org/c/coreboot/+/51445/comment/17791448_37a4842f PS3, Line 26: * Add a new raw timestamp in microseconds into timestamp_table at index 'n'. > Yeah I know, but that's one division instruction, it shouldn't really be noticeable. […] Agree that having everything in microseconds can keep things a little simpler. We would still need the new APIs as explained on the other comment. One thing that I am unsure about is some platforms that say "unknown TSC frequency". I will need to dig a little more to understand the history behind it. But, I think we should do that as a separate effort for move to microseconds since these new APIs are anyways required. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 03:01:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: enable SOL console via Kconfig
by Johnny Lin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Angel Pons, Michael Niewöhner, Tim Wawrzynczak, Morgan Jang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52091 ) Change subject: mb/ocp/deltalake: enable SOL console via Kconfig ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: On my Delta Lake SOL does not work with this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/52091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Gerrit-Change-Number: 52091 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 03:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code
by Yu-Ping Wu (Code Review) 06 Apr '21

06 Apr '21

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51918 ) Change subject: mb/google/kukui: katsu: update the EDID and initial code ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Hi Yu-Ping Wu,can u help me to cherry pick this CL to fw branch ? we need to make a FW updater. […] Done in https://crrev.com/c/2810053 -- To view, visit https://review.coreboot.org/c/coreboot/+/51918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Gerrit-Change-Number: 51918 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Apr 2021 02:54:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Lindar/Lillipup: Enable Bayhub SD card reader power-saving mode
by Kevin Chang (Code Review) 06 Apr '21

06 Apr '21

Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51623 ) Change subject: Lindar/Lillipup: Enable Bayhub SD card reader power-saving mode ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51623/comment/6ca4372f_2ba2e9b1 PS4, Line 12: TEST=Boot to OS and test with SD card function. > How did you test htis exactly? Hi Paul Checking with PCIE device register. -- To view, visit https://review.coreboot.org/c/coreboot/+/51623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Gerrit-Change-Number: 51623 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Apr 2021 02:45:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Anil Kumar K (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Bora Guvendik, Cliff Huang, Maulik V Vaghela, Subrata Banik, Bernardo Perez Priego, Anil Kumar K, Thejaswani Putta, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52140 ) Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/52140/comment/c2004074_e9a8ae85 PS1, Line 65: SOC_INTEL_ALDERLAKE_DEBUG_CONSENT > its already here https://github. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 02:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Anil Kumar K (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Maulik V Vaghela, Bernardo Perez Priego, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Bernardo Perez Priego, Anil Kumar K, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52140 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing - Enable Trace Hub - Set debugger mode to Host debugger Branch=None Test=Build and boot on ADL-M RVP. Execute BVT TAST test cases Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e --- M src/mainboard/intel/adlrvp/devicetree_m.cb M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/fsp_params.c 3 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/52140/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code
by Sunwei Li (Code Review) 06 Apr '21

06 Apr '21

Sunwei Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51918 ) Change subject: mb/google/kukui: katsu: update the EDID and initial code ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Hi Yu-Ping Wu,can u help me to cherry pick this CL to fw branch ? we need to make a FW updater.tks a lot ! -- To view, visit https://review.coreboot.org/c/coreboot/+/51918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Gerrit-Change-Number: 51918 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Apr 2021 01:49:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards
by Aseda Aboagye (Code Review) 06 Apr '21

06 Apr '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards ...................................................................... soc/intel/jasperlake: Move HECI_DISABLE_USING_SMM to mainboards Some mainboards require HECI to be enabled and having it disabled for all mainboards is problematic. This change simply moves that option to the main boards where it's necessary. BUG=b:184219504 TEST=Build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig M src/soc/intel/jasperlake/Kconfig 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52147/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 1190e969..513db2d 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -35,6 +35,7 @@ select CR50_USE_LONG_INTERRUPT_PULSES select MAINBOARD_HAS_SPI_TPM_CR50 select BOARD_GOOGLE_BASEBOARD_DEDEDE + select HECI_DISABLE_USING_SMM config BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 def_bool n diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 9bd2f5e..16ba324 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -21,6 +21,7 @@ select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU + select HECI_DISABLE_USING_SMM config MAINBOARD_DIR string diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 5f37ab1..8d36577 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -66,7 +66,6 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU
by John Zhao (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Li1 Feng, John Zhao. Hello build bot (Jenkins), Li1 Feng, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52137 to look at the new patch set (#5). Change subject: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU ...................................................................... mb/google/volteer: Add EC_HOST_EVENT_PD_MCU This change adds the EC_HOST_EVENT_PD_MCU to be dark resume source. BUG=b:183140386 TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC synchronized. AP got port partner disconnection. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I44e4075f42e9a95d26fe766489630dac0bc61b05 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/52137/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44e4075f42e9a95d26fe766489630dac0bc61b05 Gerrit-Change-Number: 52137 Gerrit-PatchSet: 5 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: timestamp: Add helper fucntions
by Julius Werner (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Aaron Durbin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/a9d7a87a_75c3518c PS3, Line 7: Add helper fucntions > Actually replace ts[X] with time_stamp_X. Sorry, I used the wrong name from the follow-up CL. I think the time_from_base in your naming is confusing, because all timestamp_add()s are relative to the base. The real difference in the one you propose is just that you're using a different scale (microseconds instead of TSC ticks). I still think this might all be easier if we first change the timestamp library to do everything in microseconds. Then you just need a timestamp_rewind_base(0 - ts[3]) with one argument, and then you can timestamp_add() all the other ones directly (which are already in microseconds to the same new base). File src/include/timestamp.h: https://review.coreboot.org/c/coreboot/+/51445/comment/cf36defb_7fb72d93 PS3, Line 26: * Add a new raw timestamp in microseconds into timestamp_table at index 'n'. > IIUC, the reason why x86 platforms store in TSC frequency is because the timestamp values are basica […] Yeah I know, but that's one division instruction, it shouldn't really be noticeable. That's the same thing that happens any time you call a stopwatch function, and all the Arm platforms do that too. I feel like we're getting so far into the woods with all these frequencies (especially with all the new APIs you're proposing) that it would really be a lot easier to just force everything to be in microseconds. -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 00:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2021