coreboot-gerrit April 2021

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Change in coreboot[master]: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Frans Hendriks, Arthur Heymans, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52152 ) Change subject: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52152/comment/38921174_f4b4d742 PS1, Line 10: configuration. I just checked, and CACHE_MRC_SETTINGS is already selected in soc/intel/braswell. So, I'd simply say: The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/52152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Gerrit-Change-Number: 52152 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 10:09:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGS
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52154 ) Change subject: mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGS ...................................................................... mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGS CACHE_MRC_SETTINGS is configured in mainboard, but should follow soc configuration. Remove select CACHE_MRC_SETTINGS in mainboard Kconfig. BUG = N/A TEST = Build and boot Portwell M107 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I528c582419fb2044f5edfd7a070785489efdf7a6 --- M src/mainboard/portwell/m107/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/52154/1 diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 3935b38..34adfd1 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -10,7 +10,6 @@ select SOC_INTEL_BRASWELL select PCIEXP_L1_SUB_STATE select HAVE_FSP_BIN - select CACHE_MRC_SETTINGS select DISABLE_HPET select HAVE_SPD_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/52154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I528c582419fb2044f5edfd7a070785489efdf7a6 Gerrit-Change-Number: 52154 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52152 ) Change subject: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS ...................................................................... mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS CACHE_MRC_SETTINGS is configured in mainboard, but should follow soc configuration. Remove select CACHE_MRC_SETTINGS in mainboard Kconfig. BUG = N/A TEST = Build and boot facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/52152/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e01f979..1c47247 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -16,7 +16,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select PCIEXP_L1_SUB_STATE select HAVE_FSP_BIN - select CACHE_MRC_SETTINGS select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/52152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Gerrit-Change-Number: 52152 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/assert.h: Use mock_assert() for ENV_TEST targets
by Jakub Czapiga (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51804 ) Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets ...................................................................... Patch Set 4: (3 comments) File src/include/assert.h: https://review.coreboot.org/c/coreboot/+/51804/comment/f509ddf3_138a576e PS3, Line 12: const char *const file, const int line); > nit: maybe declare this right next to MOCK_ASSERT() so it's more obvious where it belongs to? Good point. Done :) https://review.coreboot.org/c/coreboot/+/51804/comment/0acb1bd9_9bae5217 PS3, Line 38: mock_assert((result), (expression), (file), (line)) > You can just use __ASSERT_FILE__ and __ASSERT_LINE__ in here, no need to pass so many things. Sure, less arguments, same result :) https://review.coreboot.org/c/coreboot/+/51804/comment/7160fa79_b7f24a15 PS3, Line 71: MOCK_ASSERT(0, "BUG ENCOUNTERED", \ > Bad indentation. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Gerrit-Change-Number: 51804 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 09:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM...
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 ) Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... Patch Set 7: (1 comment) Patchset: PS4: > Will check. New patchset uploaded. -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 09:16:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: lillupup: provide additional VBT for lillipup OLED sku
by Kevin Chang (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: YH Lin, Zhuohao Lee. Hello build bot (Jenkins), YH Lin, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52150 to look at the new patch set (#2). Change subject: lillupup: provide additional VBT for lillipup OLED sku ...................................................................... lillupup: provide additional VBT for lillipup OLED sku Lillipup add two sku for OLED panel. Additional VBT is necessary to modify PWM source from VESA eDP AUX interface BUG=b:183630802 TEST=emerge-volteer coreboot-private-files-baseboard-volteer check vbt_lillipup.bin is under build folder and check in CPU log. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 --- A src/mainboard/google/volteer/variants/lindar/include/variant/sku.h M src/mainboard/google/volteer/variants/lindar/variant.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/52150/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Gerrit-Change-Number: 52150 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/assert.h: Use mock_assert() for ENV_TEST targets
by Jakub Czapiga (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Fagerburg, Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51804 to look at the new patch set (#4). Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets ...................................................................... include/assert.h: Use mock_assert() for ENV_TEST targets Some tests have to be able to catch assertion errors. Adding CMocka mock_assert() enables that. Additionally fix test_imd_create_tiered_empty(), test_full_stack() and test_incorrectly_initialized_stack() by adding missing expect_assert_failure(). Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 --- M src/include/assert.h M tests/lib/imd-test.c M tests/lib/stack-test.c 3 files changed, 20 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/51804/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Gerrit-Change-Number: 51804 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM...
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Hello build bot (Jenkins), Patrick Rudolph, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52128 to look at the new patch set (#7). Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE ASSERTION ERROR: file src/security/vboot/common.c, line 23 occurs when reading RW_MRC_CACHE. VBOOT starts in ROMSTAGE and requires workbuffer to load MRC cache. There is not enough CAR space available for vboot workbuffer. CBMEM can not be used since memory is not initialized. When VBOOT starts in ROMSTAGE, do not use MRC cache. BUG = N/A TEST = Build and boot facebook FBG1701 with VBOOT enabled and disabled. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52128/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
by Patrick Georgi (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Martin Roth, Julius Werner, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51838 ) Change subject: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > If it does the same job just as well, I'm happy with that solution too. […] Because, like your approach, it's a heuristic, and one that extends the "implied" grammar of the language we choose with a whitespace context element. Heuristics have the annoying habit of falsely triggering every now and then. There are some folks who'd rather move away from making whitespace count like that. See: golang and rust, the two newest somewhat-popular kids on the curly-braces language block, both abolishing this concept from their grammars _completely_. -- To view, visit https://review.coreboot.org/c/coreboot/+/51838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f Gerrit-Change-Number: 51838 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Apr 2021 09:12:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTIGNS depends on !VBOOT_START_IN_ROM...
by Frans Hendriks (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Arthur Heymans, Wim Vervoorn. Hello build bot (Jenkins), Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52128 to look at the new patch set (#6). Change subject: soc/intel/braswell: CACHE_MRC_SETTIGNS depends on !VBOOT_START_IN_ROMSTAGE ...................................................................... soc/intel/braswell: CACHE_MRC_SETTIGNS depends on !VBOOT_START_IN_ROMSTAGE ASSERTION ERROR: file src/security/vboot/common.c, line 23 occurs when reading RW_MRC_CACHE. VBOOT starts in ROMSTAGE and MRC cache is loaded in early stage of ROMSTAGE, before memory init. There is not enough CAR space available for vboot workbuffer. CBMEM can not be used since memory is not initialized. VBOOT uses workbuffer When VBOOT starts in ROMSTAGE, do not use MRC cache data. BUG = N/A TEST = Build and boot facebook FBG1701 with VBOOT enabled and disabled. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52128/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93 Gerrit-Change-Number: 52128 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021