coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry
by Nicola Corna (Code Review) 07 Apr '21

07 Apr '21

Nicola Corna has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52027 ) Change subject: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52027/comment/3c366885_3d1924ef PS1, Line 9: de50d39 > commit de50d39 (mb/**/cmos. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Gerrit-Change-Number: 52027 Gerrit-PatchSet: 2 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 05:47:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry
by Nicola Corna (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nicola Corna. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52027 to look at the new patch set (#2). Change subject: mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry ...................................................................... mb/sapphire/pureplatinum/cmos.default: Remove `volume` entry Following commit de50d39, remove the `volume` entry from cmos.default. Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/mainboard/sapphire/pureplatinumh61/cmos.default 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/52027/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Gerrit-Change-Number: 52027 Gerrit-PatchSet: 2 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Sathya Prakash M R (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Anil Kumar K, Meera Ravindranath. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/51408/comment/dd91857f_9402f9b6 PS7, Line 49: Alder Lake Client Platform > Does this change affect mosys or cros_config. […] Guess we need to update mosys to use the platform name. looking into that -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 05:15:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Update CpuRatio settings
by Kaiyen Chang (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Kaiyen Chang, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian. Kaiyen Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52029 ) Change subject: soc/intel/jasperlake: Update CpuRatio settings ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Why is this issue/system reset observed only on certain devices instead of all? […] Hi Karthik, The system reset would be invoked on all JSL devices while FSP finds the value of CpuRatio from m_cfg is inconsistent with the value from CPU Straps. So an extra system reset would be called while the value of flex ratio in CPU Straps is not zero currently (before applying this patch). In addition, the CpuRatio would be set back to zero so that the change of flex ratio in CPU Straps would not take affect for memory training. The hang issue caused by this extra reset is another issue and we will investigate it later. Thanks, Kaiyen -- To view, visit https://review.coreboot.org/c/coreboot/+/52029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5 Gerrit-Change-Number: 52029 Gerrit-PatchSet: 4 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Evan Green <evgreen(a)chromium.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 04:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Maulik V Vaghela, Subrata Banik, Bernardo Perez Priego, Thejaswani Putta, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52140 ) Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/52140/comment/a1093581_88c3a538 PS2, Line 81: SOC_INTEL_DEBUG_CONSENT I don't think this should be enabled by default. It should be enabled at the mainboard level only if required. https://review.coreboot.org/c/coreboot/+/52140/comment/be63bda9_24a042aa PS2, Line 276: 7 Why is this being changed from 3 to 7? This conflicts with the comment on lines 274-275. File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52140/comment/8bd56644_714c9a60 PS2, Line 129: /* Disable DCI DBC mode */ : m_cfg->DciDbcMode = 0; : : /* Disable platform debugger support */ : m_cfg->DciUsb3TypecUfpDbg = 0; : : /* Set trace debug mode to Host Debugger Mode */ : m_cfg->PchTraceHubMode = 2; : m_cfg->CpuTraceHubMode = 2; I think this needs to be handled better. Based on your changes it looks like this is applicable only for CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT == 7. If that is the case, then we should add appropriate checks for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 04:02:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change GPP_D15/D16 default to low
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52148 ) Change subject: mb/google/brya: Change GPP_D15/D16 default to low ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52148/comment/56147469_b37f1144 PS2, Line 9: WFC Camera driver will control the power sequence. > Just a note that this is currently not done. […] yes, this is for Meera ;p -- To view, visit https://review.coreboot.org/c/coreboot/+/52148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Gerrit-Change-Number: 52148 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 03:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change GPP_D15/D16 default to low
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52148 ) Change subject: mb/google/brya: Change GPP_D15/D16 default to low ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52148/comment/d6fec464_3a72ba1d PS2, Line 9: WFC Camera driver will control the power sequence. Just a note that this is currently not done. So, once the required ACPI support is enabled, the power sequencing should be taken care of. -- To view, visit https://review.coreboot.org/c/coreboot/+/52148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Gerrit-Change-Number: 52148 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 03:49:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change GPP_D15/D16 default to low
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello Furquan Shaikh, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52148 to look at the new patch set (#2). Change subject: mb/google/brya: Change GPP_D15/D16 default to low ...................................................................... mb/google/brya: Change GPP_D15/D16 default to low WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/52148/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Gerrit-Change-Number: 52148 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Change GPP_D15/D16 default to low
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52148 ) Change subject: mb/google/brya: Change GPP_D15/D16 default to low ...................................................................... mb/google/brya: Change GPP_D15/D16 default to low WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/52148/1 diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 6482b9c..dd33b49 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -148,9 +148,9 @@ /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Gerrit-Change-Number: 52148 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Configure UART0 gpio in early stage
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Mathew King, Paul Menzel. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52122 ) Change subject: mb/google/mancomb: Configure UART0 gpio in early stage ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52122/comment/1cb39ad9_cd544325 PS1, Line 8: > Why? What behavior is improved? We need log start for early stage. -- To view, visit https://review.coreboot.org/c/coreboot/+/52122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Gerrit-Change-Number: 52122 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 07 Apr 2021 03:18:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit April 2021