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Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Patchset:
PS2:
I've tested this patch and I see both NVMe and WiFi working. I'm fine landing it for now so we can unblock peripheral testing.
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/77995b84_70190b37
PS1, Line 54: HIGH
> Reasoning for my comment: Violating timings for PCIe can result in downstream device not being enume […]
Just for my own knowledge, what's the correct way to handle these timings constraints? The i2c ACPI driver allows specifying the GPIOs and delays as part of the device tree. Is there a similar device tree PCI driver that will handle toggling the pins?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52144 )
Change subject: ec/lenovo/h9/acpi: fix wrong calculation
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Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52144/comment/b4ba288a_46e344c1
PS1, Line 7: h9
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h9 ---> h8
https://review.coreboot.org/c/coreboot/+/52144/comment/40b35d25_d4589354
PS1, Line 9: commit 5461662
this isn't the right commit. Also how about using a Fixes tag:
Fixes: commit 81d55cf6d62ac710df030fc02dd3ca00f3d80405
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Change subject: mb/google/guybrush: Unmask eSPI keyboard IRQ
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Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/mainboard.c:
https://review.coreboot.org/c/coreboot/+/52143/comment/af266e61_949859a0
PS1, Line 118: /* Unmask eSPI IRQ 1 and 12 */
> nit: It'd be helpful to comment what these IRQS map to.
Done
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Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/1e3c1a10_acf45f74
PS1, Line 54: HIGH
> Not in my experience, no. […]
Reasoning for my comment: Violating timings for PCIe can result in downstream device not being enumerated in some cases which can result in developers debugging issues that wouldn't occur if it was done the right way. It helps with the bringup rather than hurt. This was one of the things that had caused hacks to be added for zork and also had resulted in missed hardware changes until much later. That was the reason I raised this concern to ensure:
1. Either the timings are handled correctly here or
2. The bug you raised captured details about exactly what needs to be done so that it can be picked up by anyone who has cycles.
I will mark this as resolved to let you continue.
https://review.coreboot.org/c/coreboot/+/52115/comment/d0fad776_22441a6e
PS1, Line 169: /* EN_PP3300_WLAN */
> Yes, I absolutely agree with you. I'll get to that when I'm working on the other bug.
Ack
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