coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 19: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/b4cccbf0_62883d72 PS19, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > hm, I guess I'm used to userspace behavior 😄 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 19 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 19:11:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lillupup: provide additional VBT for lillipup OLED sku
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Kevin Chang, Nick Vaccaro, YH Lin, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52150 ) Change subject: lillupup: provide additional VBT for lillipup OLED sku ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: This line: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… should be changed in this patchset to be just: ``` ramstage-y += variant.c ``` along with changing get_wifi_sar_cbfs_filename to: ``` const char *get_wifi_sar_cbfs_filename(void) { if (CONFIG(FW_CONFIG)) { if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, WIFI_SAR_ID_0))) return "wifi_sar_0.hex"; else if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, WIFI_SAR_ID_1))) return "wifi_sar_1.hex"; } return WIFI_SAR_CBFS_DEFAULT_FILENAME; } ``` because variant.c doesn't always depend on fw_config anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/52150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Gerrit-Change-Number: 52150 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 19:09:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 19: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/d13e91d4_1013035a PS19, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > It will either return a valid pointer between the heap linker symbols (from calling malloc() before […] hm, I guess I'm used to userspace behavior 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 19 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 19:08:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 19: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/2a3bbcd8_8b7de68b PS19, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > Can calloc return null? It will either return a valid pointer between the heap linker symbols (from calling malloc() before zeroing), or malloc/memalign() will die() if it cannot allocate memory. -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 19 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 19:03:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add function to lpc_lib to return PIRQ routing
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Angel Pons, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50858 ) Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > Did you apply CB:50857 as well? PIRQ_* are redefined somewhere in the last few patchsets of 50857 as Angel mentioned. -- To view, visit https://review.coreboot.org/c/coreboot/+/50858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Gerrit-Change-Number: 50858 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 19:01:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
by Tim Wawrzynczak (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 ) Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/51846/comment/efe944c2_3d0dc901 PS2, Line 316: /* : * SLP_S3 Minimum Assertion Width Policy : * 1 = 60us : * 2 = 1ms : * 3 = 50ms (default) : * 4 = 2s : */ : uint8_t PchPmSlpS3MinAssert; : : /* : * SLP_S4 Minimum Assertion Width Policy : * 1 = 1s (default) : * 2 = 2s : * 3 = 3s : * 4 = 4s : */ : uint8_t PchPmSlpS4MinAssert; : : /* : * SLP_SUS Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 500ms : * 3 = 1s : * 4 = 4s (default) : */ : uint8_t PchPmSlpSusMinAssert; : : /* : * SLP_A Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 4s : * 3 = 98ms : * 4 = 2s (default) : */ : uint8_t PchPmSlpAMinAssert; : : /* : * PCH PM Reset Power Cycle Duration : * 0 = 4s (default) : * 1 = 1s : * 2 = 2s : * 3 = 3s : * 4 = 4s : * : * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the : * stretch duration programmed in the following registers: : * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) : * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) : * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) : * - PM_CFG.SLP_LAN_MIN_ASST_WDTH : */ : uint8_t PchPmPwrCycDur; > Conversion might be required one way or the other. […] Good point, these bits are all well-defined in the EDS, just need the double programming for now 😞 -- To view, visit https://review.coreboot.org/c/coreboot/+/51846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91bd49d35f80fbde4aa3b7ec816217d2c1a5853e Gerrit-Change-Number: 51846 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:59:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 19: Code-Review+1 (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/55f00ba1_0f7c7dd8 PS19, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); Can calloc return null? -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 19 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:58:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add function to lpc_lib to return PIRQ routing
by Angel Pons (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50858 ) Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > This doesn't build on top-of-tree chromeos coreboot. […] Did you apply CB:50857 as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/50858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Gerrit-Change-Number: 50858 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:56:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Nick Vaccaro, Sridhar Siricilla, Meera Ravindranath, Patrick Rudolph, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51846 ) Change subject: soc/intel/alderlake: Configure FSP UPDs for minimum assertion widths ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/51846/comment/a568b770_29097147 PS2, Line 316: /* : * SLP_S3 Minimum Assertion Width Policy : * 1 = 60us : * 2 = 1ms : * 3 = 50ms (default) : * 4 = 2s : */ : uint8_t PchPmSlpS3MinAssert; : : /* : * SLP_S4 Minimum Assertion Width Policy : * 1 = 1s (default) : * 2 = 2s : * 3 = 3s : * 4 = 4s : */ : uint8_t PchPmSlpS4MinAssert; : : /* : * SLP_SUS Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 500ms : * 3 = 1s : * 4 = 4s (default) : */ : uint8_t PchPmSlpSusMinAssert; : : /* : * SLP_A Minimum Assertion Width Policy : * 1 = 0ms : * 2 = 4s : * 3 = 98ms : * 4 = 2s (default) : */ : uint8_t PchPmSlpAMinAssert; : : /* : * PCH PM Reset Power Cycle Duration : * 0 = 4s (default) : * 1 = 1s : * 2 = 2s : * 3 = 3s : * 4 = 4s : * : * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the : * stretch duration programmed in the following registers: : * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) : * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) : * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) : * - PM_CFG.SLP_LAN_MIN_ASST_WDTH : */ : uint8_t PchPmPwrCycDur; > Other option would be to just use the enums as symbolic only, and leave their values specified as th […] Conversion might be required one way or the other. This configuration has to be performed in coreboot before FSP runs because coreboot could trigger a global reset for reasons like CSE RO->RW jump. So, we need to use the same configuration in coreboot as well as to pass into FSP UPD (I think we should ask Intel to add a UPD option indicating do not change min assert values). But, until then, we can use the enum as you suggested and configure the register in coreboot and convert that into appropriate UPDs for FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/51846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91bd49d35f80fbde4aa3b7ec816217d2c1a5853e Gerrit-Change-Number: 51846 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:54:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add function to lpc_lib to return PIRQ routing
by Nick Vaccaro (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Tim Wawrzynczak. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50858 ) Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: This doesn't build on top-of-tree chromeos coreboot. coreboot-9999: src/soc/intel/common/block/lpc/lpc_lib.c:309:3: error: array index in initializer exceeds array bounds coreboot-9999: [PIRQ_H] = PCH_IRQ11, -- To view, visit https://review.coreboot.org/c/coreboot/+/50858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Gerrit-Change-Number: 50858 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Apr 2021 18:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2021