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Change subject: libpayload: i8042: Enable keyboard translation by defualt on exit
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Would need to just use CHROMEOS since this is inside libpayload kconfig, but that could certainly wo […]
Based on the discussion on CB:47594, it looks like it is safe to set the default to set2+translate. So, going with a default of 'y' seems fine to me.
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Change subject: amd/cezanne: Add telemetry setting to UPD
......................................................................
Patch Set 1:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/52733/comment/091e7732_a70eda7d
PS1, Line 106: 0x04C7
> We have SO many unaligned fields. […]
oh, yeah there are more other unaligned fields than i thought; looks like i didn't remember to check that when integrating the upd headers for cezanne. i'd avoid moving already used upd fields around, since the binary interface changes are always a bit of a pain, so i'd probably avoid that if possible. things we should write down somewhere as a check-list to not make the same mistake in a next generation.
not sure what the best action would be now though. it would be nicer to have everything aligned, but i'm also not completely convinced that it's worth breaking the binary interface
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Change subject: cpu/x86/mtrr: Prefer keeping WRCOMB requests to reserving MTRRs for OS
......................................................................
Patch Set 2: Code-Review+2
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Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52742 )
Change subject: cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE
......................................................................
cpu/x86/smm: increase SMM_CODE_SEGMENT_SIZE
Increase SMM_CODE_SEGMENT_SIZE to 0x10f00 to accomodate
for the permanent SMM handler's size on tiger lake.
BUG=b:186661594
TEST=`emerge-volteer coreboot chromeos-bootimage`, flash voxel
and verify it boots to kernel.
Change-Id: Ie9fdae7cdf812d92a4d3b61368de884f4e55aa3a
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/cpu/x86/smm/smm_module_loader.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52742/1
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index e3b8417..2e046f3 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -10,7 +10,7 @@
#include <security/intel/stm/SmmStm.h>
#define FXSAVE_SIZE 512
-#define SMM_CODE_SEGMENT_SIZE 0x10000
+#define SMM_CODE_SEGMENT_SIZE 0x10f00
/* FXSAVE area during relocation. While it may not be strictly needed the
SMM stub code relies on the FXSAVE area being non-zero to enable SSE
instructions within SMM mode. */
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86/mtrr: Prefer keeping WRCOMB requests to reserving MTRRs for OS
......................................................................
cpu/x86/mtrr: Prefer keeping WRCOMB requests to reserving MTRRs for OS
Given that keeping 2 MTRRs reserved for the OS is more of an advisory,
the MTRR calculation should fulfill WRCOMB requests if possible instead
of reserving them.
Change-Id: I108c743d25baaeae1860732601cc7abda2f05932
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/cpu/x86/mtrr/mtrr.c
1 file changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52642/2
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Change subject: cpu/x86/mtrr: Prefer keeping WRCOMB requests to reserving MTRRs for OS
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Needs update?
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Change subject: cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS
......................................................................
Patch Set 8: Code-Review+2
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