Attention is currently required from: Furquan Shaikh, Kyösti Mälkki.
Hello build bot (Jenkins), Furquan Shaikh, Mario Scheithauer, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52721
to look at the new patch set (#4).
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data
hold time on mainboard level to get a proper timing which takes the bus
load into account. Giving these values the driver computes the needed
timings correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
5 files changed, 44 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52721/4
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52721 )
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52721/comment/13566189_b85dc482
PS2, Line 13: computes the needed timings correctly.
> nit: Depends of the order things are submitted if the note about defaults is still correct or not.
Yes, I have changed the message.
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Attention is currently required from: Furquan Shaikh, Werner Zeh.
Hello build bot (Jenkins), Furquan Shaikh, Mario Scheithauer, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52721
to look at the new patch set (#3).
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data hold
time on mainboard level to get a proper timing which takes the bus load
into account. Giving these values the driver computes the needed timings
correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
5 files changed, 44 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52721/3
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52693 )
Change subject: soc/intel/skylake: Add microcodes for Coffee Lake CPUs
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52693/comment/0ca48f67_f0decaef
PS5, Line 7: Coffee Lake
Rather write Amber Lake here to avoid confusions with soc/intel/cannonlake
File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/c/coreboot/+/52693/comment/353d7f9c_2a814cac
PS5, Line 314: COFFEELAKE
AMBERLAKE
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Attention is currently required from: Patrick Rudolph.
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52777
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Remove unuseful help texts
......................................................................
soc/intel/cannonlake: Remove unuseful help texts
Remove unuseful help texts since they don't add any more value.
Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/52777/2
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52777 )
Change subject: soc/intel/cannonlake: Remove unuseful help texts
......................................................................
soc/intel/cannonlake: Remove unuseful help texts
Remove unuseful help texts since they don't add any more value and the
names of their options are self explaining.
Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/52777/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 1d0fe47..7e5d4be 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -7,8 +7,6 @@
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
- help
- Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE
bool
@@ -16,8 +14,6 @@
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
- help
- Intel Whiskeylake support
config SOC_INTEL_COMETLAKE_COMMON
bool
@@ -25,8 +21,6 @@
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
- help
- Intel Cometlake support
config SOC_INTEL_COMETLAKE_1
bool
@@ -46,8 +40,6 @@
config SOC_INTEL_CANNONLAKE_PCH_H
bool
- help
- Choose this option if you have a PCH-H chipset.
if SOC_INTEL_CANNONLAKE_BASE
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