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Change subject: soc/mediatek/mt8192: devapc: Add ADSP domain setting
......................................................................
Patch Set 2: Code-Review+2
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52565 )
Change subject: mb/google/dedede/var/galith: Support Wifi SAR for DVT phase
......................................................................
mb/google/dedede/var/galith: Support Wifi SAR for DVT phase
Because galith/gallop both non-suport tablet mode,
remove un-use fw_config conditional.
BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: Ic9bb76c207ef033f81ecdd57849535b8ac8d13ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52565
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/dedede/variants/galtic/variant.c
1 file changed, 1 insertion(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Frank Chu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c
index 92aa176..72d91ee 100644
--- a/src/mainboard/google/dedede/variants/galtic/variant.c
+++ b/src/mainboard/google/dedede/variants/galtic/variant.c
@@ -5,7 +5,5 @@
const char *get_wifi_sar_cbfs_filename(void)
{
- if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED)))
- return "wifi_sar-galtic.hex";
- return WIFI_SAR_CBFS_DEFAULT_FILENAME;
+ return "wifi_sar-galtic.hex";
}
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52642 )
Change subject: cpu/x86/mtrr: Prefer keeping WRCOMB requests to reserving MTRRs for OS
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Nico, I think you worked on MTRR allocation at some point. Any opinion on this?
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52548 )
Change subject: cpu/x86/msr: introduce helpers msr_read, msr_write
......................................................................
cpu/x86/msr: introduce helpers msr_read, msr_write
The existing helpers for reading/writing MSRs (rdmsr, wrmsr) require use
of the struct `msr_t`, which splits the MSR value into two 32 bit parts.
In many cases, where simple 32 bit or 64 bit values are written, this
bloats the code by unnecessarly having to use that struct.
Thus, introduce the helpers `msr_read` and `msr_write`, which take or
return `uint64_t` values, so the code condenses to a single line or two,
without having to deal with `msr_t`.
Example 1:
~~~
msr_t msr = {
.lo = read32((void *)(uintptr_t)0xfed30880),
.hi = 0,
};
msr.lo |= 1;
wrmsr(0x123, msr);
~~~
becomes
~~~
uint32_t foo = read32((void *)(uintptr_t)0xfed30880);
msr_write(0x123, foo | 1)
~~~
Example 2:
~~~
msr_t msr = rdmsr(0xff);
uint64_t msr_val = (msr.hi << 32) | msr.lo;
~~~
becomes
~~~
uint64_t msr_val = msr_read(0xff);
~~~
Change-Id: I27333a4bdfe3c8cebfe49a16a4f1a066f558c4ce
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52548
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/include/cpu/x86/msr.h
1 file changed, 26 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Felix Held: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, but someone else must approve
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 5ae3ddf..bc367d7 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -301,6 +301,32 @@
}
/**
+ * Helper for reading a MSR
+ *
+ * @param[in] reg The MSR.
+ */
+static inline uint64_t msr_read(unsigned int reg)
+{
+ msr_t msr = rdmsr(reg);
+ return (((uint64_t)msr.hi << 32) | msr.lo);
+}
+
+/**
+ * Helper for writing a MSR
+ *
+ * @param[in] reg The MSR.
+ * @param[in] value The value to be written to the MSR.
+ */
+static inline void msr_write(unsigned int reg, uint64_t value)
+{
+ msr_t msr = {
+ .lo = (unsigned int)value,
+ .hi = (unsigned int)(value >> 32)
+ };
+ wrmsr(reg, msr);
+}
+
+/**
* Helper for (un)setting MSR bitmasks
*
* @param[in] reg The MSR.
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52726 )
Change subject: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI
......................................................................
mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Brya uses CBI to store dram part number. So enable the config.
BUG=b:186571840
BRANCH=none
TEST=dmidecode -t 17 can show the dram part number.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index d53065f..567f15d 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -31,6 +31,7 @@
select SYSTEM_TYPE_LAPTOP
config CHROMEOS
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52745 )
Change subject: device/dram: Add support for LPDDR4 4266
......................................................................
Patch Set 3:
(1 comment)
File src/device/dram/ddr4.c:
https://review.coreboot.org/c/coreboot/+/52745/comment/1f5ed90b_26f6c660
PS3, Line 22: lpddr4_speed_grade
This entire file deals with DDR4 specifically. I don't think it is correct to add LPDDR4 to the same file. It would be better to do one of the following:
1. Add a separate file lpddr4.c and implement the required functions.
2. If you want to take advantage of the common function `speed_mhz_to_reported_mts`, then you can expose that as an API:
`uint16_t speed_mhz_to_reported_mts(enum ddr_type, uint16_t speed_mhz)`
This can be implemented in ddr_common.c and it can make use of appropriate tables based on ddr_type.
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