Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52779 )
Change subject: mainboard/pcengines/apu1/OemCustomize.c: make AGESA AmdInitPost happy
......................................................................
mainboard/pcengines/apu1/OemCustomize.c: make AGESA AmdInitPost happy
Bank interleaving does not work on this platform, disable it.
AmdIntPost returns success thanks to this setting.
TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca
---
M src/mainboard/pcengines/apu1/OemCustomize.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52779/1
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index d6edf03..254947c 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -101,4 +101,6 @@
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+ /* Bank interleaving is not supported on this platform */
+ InitPost->MemConfig.EnableBankIntlv = FALSE;
}
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Ravindra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51795 )
Change subject: soc/intel/alderlake: Enable HWP CPPC support in CB
......................................................................
Patch Set 8:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51795/comment/bd077158_7fb32b42
PS1, Line 7: HGS
> coreboot don't expected to publish anything for HGS+ and what you have done is HWP ACPI table.
corrected the commit message
Commit Message:
https://review.coreboot.org/c/coreboot/+/51795/comment/721fe39a_25718bc1
PS2, Line 7: [adl-p pre-CEP] HGS+ and ITBM support in CB
> Please use a statement. […]
Ack
Patchset:
PS7:
> Also mark all comments as Resolved
all comments resolved. Marked branch as public.
Patchset:
PS8:
all comments resolved and commit message updated.
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Hello build bot (Jenkins), Tim Wawrzynczak, Alex Levin, Nathan D Ciobanu, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51795
to look at the new patch set (#8).
Change subject: soc/intel/alderlake: Enable HWP CPPC support in CB
......................................................................
soc/intel/alderlake: Enable HWP CPPC support in CB
Kconfig change which enables the hwp cppc acpi support is to get the
maximum performance of each CPU to check and enable Intel Turbo Boost
Max Technology.
BUG=none
BRANCH=none
TEST=check GCPC and CPC generated in acpi tables for each CPU
Change-Id: I5d93774e8025466f1911cf77459910fe872bfcc8
Signed-off-by: ravindr1 <ravindra(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51795/8
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Change subject: tests: enable code coverage for unit tests
......................................................................
Patch Set 3:
(2 comments)
File tests/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/52444/comment/9af40bed_26158f50
PS3, Line 165: build/tests
I think you can use $(testobj) instead.
If you want to enable one to change coverage obj directory you can introduce variable e.g. TEST_OBJ_DIR (command-line argument) and use it to overwrite $(testobj) at the beginning of this makefile.
https://review.coreboot.org/c/coreboot/+/52444/comment/23033fc1_23b47d18
PS3, Line 205: Generate a code coverage report
This might be misleading. This target does not only generate coverage report but builds all tests with --coverage flag. I think this description should include all of its behavior.
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Change subject: Makefile,tests: Move cmocka checkout into top level Makefile
......................................................................
Patch Set 1: Code-Review+2
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Change subject: [RFC] soc/intel/skylake: Introduce new method for setting device states
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/skylake/fspdevmap.h:
https://review.coreboot.org/c/coreboot/+/52493/comment/8f738b64_d1363a4a
PS9, Line 9: const uint8_t inverted;
> since the FSP option names might differ in their name length a lot, which makes it less readable.
When moving the fsp option to pos 1, it wouldn't look that bad. We might still keep the inverted field always, like Angel proposed.
const struct device_fspoption_map devmap[] = {
{ ¶ms->Device4Enable, SA_DEVFN_TS, .inverted=1, },
{ &tconfig->ChapDeviceEnable, SA_DEVFN_GMM, .inverted=1, },
{ &tconfig->sdfsdfsdfsdfsdfsdfsdsdfdf, SA_DEVFN_GMM .inverted=1, },
{ &tconfig->sdfsdfsdfsdfsdfsdfsdsdfdfggg, SA_DEVFN_XXXXXX, .inverted=1, },
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Change subject: soc/intel/skylake: Clean up root port structs
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/52627/comment/f262a3c5_0ab11788
PS2, Line 35: static const struct pcie_rp_group pch_rp_groups[] = {
: #if CONFIG(SKYLAKE_SOC_PCH_H)
: { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
: { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
: /* Sunrise Point PCH-H actually only has 4 ports in the
: third group. But that would require a runtime check
: and probing 4 non-existent ports shouldn't hurt. */
: { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
: #else
: { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
: { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
: #endif
:
> I don't think we should do it like that because it makes things even more confusing.
why confusing? the third controller is only there on PCH-H
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Change subject: soc/intel/skylake: Add microcodes for Coffee Lake CPUs
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52693/comment/47905a22_82d2ef70
PS5, Line 7: Coffee Lake
> Rather write Amber Lake here to avoid confusions with soc/intel/cannonlake
The CPUs are Coffee Lake, though. They are not Amber Lake.
File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/c/coreboot/+/52693/comment/53e4c764_fa4dda05
PS5, Line 314: COFFEELAKE
> AMBERLAKE
The CPUs are not Amber Lake.
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