Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52793 )
Change subject: console: CONSOLE_SPI_FLASH depends on BOOT_DEVICE_SPI_FLASH
......................................................................
console: CONSOLE_SPI_FLASH depends on BOOT_DEVICE_SPI_FLASH
Change-Id: Ibfdbca02259a723029260dfea9f36b325414b7d3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/console/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52793/1
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 548b701..8dcfd4d 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -260,6 +260,7 @@
config CONSOLE_SPI_FLASH
bool "SPI Flash console output"
default n
+ depends on BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if !COMMON_CBFS_SPI_WRAPPER
help
Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area
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Gerrit-Change-Id: Ibfdbca02259a723029260dfea9f36b325414b7d3
Gerrit-Change-Number: 52793
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52787
to look at the new patch set (#2).
Change subject: nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
......................................................................
nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/mainboard/google/beltino/Makefile.inc
M src/mainboard/intel/baskingridge/Makefile.inc
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
10 files changed, 4 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/52787/2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52787 )
Change subject: nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/emulation/qemu-i440fx/Kconfig:
https://review.coreboot.org/c/coreboot/+/52787/comment/3e95f30f_6811d121
PS1, Line 22: VBOOT_SEPARATE_VERSTAGE
maybe this one is not too smart as the bootblock size is limited to 64K by the SOUTHBRIDGE_INTEL_I82371EB. I'll check on the sizes
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Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Sugnan Prabhu S, Bernardo Perez Priego, Ronak Kanabar.
Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Sugnan Prabhu S, Subrata Banik, Bernardo Perez Priego, Ronak Kanabar,
I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/intel/adlrvp/early_gpio.c
1 file changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52270/10
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