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Change subject: [RFC] device/pnp: do not warn for generic unassigned ressources
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
AFAICS, declaring these pseudo resources has only one effect:
We can print the warning.
If we don't print the warning anymore, shouldn't we remove
all mentions of `PNP_MSC*`? Or actually start with that,
remove the declarations in the sio drivers if a register
doesn't have to be configured.
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Change subject: soc/intel/skylake: Clean up root port structs
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/skylake/chip.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118076):
https://review.coreboot.org/c/coreboot/+/52627/comment/3dafc1f6_fa60e3d7
PS3, Line 37: #if CONFIG(SKYLAKE_SOC_PCH_H)
braces {} are not necessary for single statement blocks
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Change subject: soc/intel/cannonlake: Clean up root port structs
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/cannonlake/chip.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118077):
https://review.coreboot.org/c/coreboot/+/52628/comment/3aed17c9_bca9fafa
PS4, Line 22: #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
braces {} are not necessary for single statement blocks
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Change subject: soc/intel/skylake: Clean up root port structs
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52627/comment/47381482_e68f1d3a
PS2, Line 9: correct struct with
: root port count
> PCIe root port groups struct?
Done
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/52627/comment/7887fc6f_10b56cf2
PS2, Line 35: static const struct pcie_rp_group pch_rp_groups[] = {
: #if CONFIG(SKYLAKE_SOC_PCH_H)
: { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
: { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
: /* Sunrise Point PCH-H actually only has 4 ports in the
: third group. But that would require a runtime check
: and probing 4 non-existent ports shouldn't hurt. */
: { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
: #else
: { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
: { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
: #endif
:
> we already have one PCH with only 4 ports in group 3 (PCIE_2): KBL. […]
I don't think we should do it like that because it makes things even more confusing.
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Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cannonlake: Clean up root port structs
......................................................................
soc/intel/cannonlake: Clean up root port structs
Currently, a runtime check is used for choosing the PCIe root port
groups struct in order to update the devicetree. Since this can be
done at compile time, merge these structs into one using a preprocessor
if-condition and remove that runtime check.
Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/cannonlake/chip.c
1 file changed, 4 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52628/4
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Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52627
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Clean up root port structs
......................................................................
soc/intel/skylake: Clean up root port structs
Currently, a runtime check is used for choosing the PCIe root port
groups struct in order to update the devicetree. Since this can be
done at compile time, merge these structs into one using a preprocessor
if-condition and remove that runtime check.
Change-Id: I0d5155356bd302ef938c76eb60688276fec67502
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/skylake/chip.c
1 file changed, 6 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/52627/3
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Change subject: device: Switch pci_dev_is_wake_source to take pci_devfn_t
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/jasperlake/elog.c:
https://review.coreboot.org/c/coreboot/+/52765/comment/93a194ab_04ac6994
PS2, Line 15: pci_devfn_t
> You mean `unsigned int` instead of something that makes you think it's an MMCONF-compatible devfn? ? […]
That's right.
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Change subject: soc/intel/cannonlake: Clean up root port structs
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
+2 but let others have a look
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Change subject: src/acpi: Add APEI EINJ support
......................................................................
Patch Set 12: Code-Review+2
(2 comments)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/49286/comment/9a898325_f2f59af7
PS11, Line 993:
> I haven't been able to test anything with this, but I'm hoping others can add it once they need it. […]
Ack
https://review.coreboot.org/c/coreboot/+/49286/comment/d0ca895c_e2edc8e0
PS11, Line 1001: /* EINJ (Error Injection Table) */
: typedef struct acpi_gen_regaddr1 {
: u8 space_id; /* Address space ID */
: u8 bit_width; /* Register size in bits */
: u8 bit_offset; /* Register bit offset */
: u8 access_size; /* Access size since ACPI 2.0c */
: u64 addr; /* Register address */
: } __packed acpi_addr64_t;
:
> Yes, that's correct but it matches the ACPI spec. The same comment as above applies here. […]
It depends on architecture endianness (obviously x86 this is fine)
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