coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/cannonlake: Clean up root port structs
by build bot (Jenkins) (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52628 ) Change subject: soc/intel/cannonlake: Clean up root port structs ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/cannonlake/chip.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118074): https://review.coreboot.org/c/coreboot/+/52628/comment/85f9986b_1149e8df PS3, Line 22: #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/52628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9 Gerrit-Change-Number: 52628 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:57:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Move external oscillator config away from common
by Karthik Ramasubramanian (Code Review) 30 Apr '21

30 Apr '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52771 ) Change subject: soc/amd/common: Move external oscillator config away from common ...................................................................... soc/amd/common: Move external oscillator config away from common The usage of external oscillator has got nothing to do with Audio Co-processor (ACP). Hence move it out of common config and put it into the SoC config where it is being used. BUG=None TEST=Build Dalboz and Vilboz mainboards. Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/zork/variants/vilboz/variant.c M src/soc/amd/common/block/include/amdblocks/acp.h M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fch.c 4 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52771/1 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index df82698..43ca0e5 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -45,7 +45,7 @@ /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ if (variant_has_wwan()) { - soc_cfg->common_config.acp_config.acp_i2s_use_external_48mhz_osc = 1; + soc_cfg->acp_i2s_use_external_48mhz_osc = 1; /* eDP phy tuning settings */ soc_cfg->edp_phy_override = ENABLE_EDP_TUNINGSET; diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h index f091c05..36edfa1 100644 --- a/src/soc/amd/common/block/include/amdblocks/acp.h +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -17,9 +17,6 @@ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ u8 acp_pme_enable; - - /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ - bool acp_i2s_use_external_48mhz_osc; }; #endif /* AMD_COMMON_ACP_H */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index d59a4c8..d2ce1bc 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -257,6 +257,8 @@ /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; /* eDP phy tuning settings */ uint16_t edp_phy_override; diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index a871ccf..e1c0eba 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -90,12 +90,12 @@ void sb_clk_output_48Mhz(void) { u32 ctrl; - const struct soc_amd_common_config *cfg = soc_get_common_config(); + const struct soc_amd_picasso_config *cfg = config_of_soc(); ctrl = misc_read32(MISC_CLK_CNTL1); /* If used external clock source for I2S, disable the internal clock output */ - if (cfg->acp_config.acp_i2s_use_external_48mhz_osc && - cfg->acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM) + if (cfg->acp_i2s_use_external_48mhz_osc && + cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM) ctrl &= ~BP_X48M0_OUTPUT_EN; else ctrl |= BP_X48M0_OUTPUT_EN; -- To view, visit https://review.coreboot.org/c/coreboot/+/52771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Gerrit-Change-Number: 52771 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Clean up root port structs
by Felix Singer (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52628 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Clean up root port structs ...................................................................... soc/intel/cannonlake: Clean up root port structs Currently, a runtime check is used for choosing the correct struct with root port count in order to update the devicetree. Since this can be done at compile time, merge these structs into one using a preprocessor if-condition and remove that runtime check. Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52628/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9 Gerrit-Change-Number: 52628 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ChromeOS: Separate NVS from global GNVS
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Lance Zhao, Angel Pons, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51638 ) Change subject: ChromeOS: Separate NVS from global GNVS ...................................................................... Patch Set 4: (1 comment) File src/acpi/gnvs.c: https://review.coreboot.org/c/coreboot/+/51638/comment/08b62c48_4e4055d0 PS4, Line 43: chromeos_init_chromeos_acpi > Looks like I somehow removed [WIP] with rebase. […] Sorry gotcha. You mean split ChromeOS NVS init from the GNVS/DNVS ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Gerrit-Change-Number: 51638 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:54:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Furquan Shaikh, Selma Bensaid, Paul Menzel, Meera Ravindranath, Angel Pons, Subrata Banik, Ronak Kanabar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/54775f7d_cb7c6bbc PS11, Line 230: What about TBT0BAR, etc.? -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 11 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Clean up root port structs
by Michael Niewöhner (Code Review) 30 Apr '21

30 Apr '21

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Change in coreboot[master]: soc/intel/cannonlake: Clean up root port structs
by Michael Niewöhner (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52628 ) Change subject: soc/intel/cannonlake: Clean up root port structs ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/chip.c: https://review.coreboot.org/c/coreboot/+/52628/comment/1ed19945_ab111c5b PS2, Line 19: static const struct pcie_rp_group pch_rp_groups[] = { : #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, : #else : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : #endif : { 0 } : }; : what about this, like on the parent? static const struct pcie_rp_group pch_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, #endif { 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9 Gerrit-Change-Number: 52628 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:45:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Clean up root port structs
by Michael Niewöhner (Code Review) 30 Apr '21

30 Apr '21

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Change in coreboot[master]: device: Switch pci_dev_is_wake_source to take pci_devfn_t
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52765 ) Change subject: device: Switch pci_dev_is_wake_source to take pci_devfn_t ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/jasperlake/elog.c: https://review.coreboot.org/c/coreboot/+/52765/comment/f389da2e_36a276ca PS2, Line 15: pci_devfn_t > This will need update too here and in other SoC elog.c files. Can be pushed as a separate change. You mean `unsigned int` instead of something that makes you think it's an MMCONF-compatible devfn? 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/52765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Gerrit-Change-Number: 52765 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:44:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Clean up root port structs
by Michael Niewöhner (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52627 ) Change subject: soc/intel/skylake: Clean up root port structs ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52627/comment/f866b218_bc9340f5 PS2, Line 35: static const struct pcie_rp_group pch_rp_groups[] = { : #if CONFIG(SKYLAKE_SOC_PCH_H) : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : /* Sunrise Point PCH-H actually only has 4 ports in the : third group. But that would require a runtime check : and probing 4 non-existent ports shouldn't hurt. */ : { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, : #else : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, : #endif : we already have one PCH with only 4 ports in group 3 (PCIE_2): KBL. we can do the same for -LP like this: static const struct pcie_rp_group pch_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, #if CONFIG(SKYLAKE_SOC_PCH_H) /* Sunrise Point PCH-H actually only has 4 ports in the third group. But that would require a runtime check and probing 4 non-existent ports shouldn't hurt. */ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, #endif { 0 } }; I both cases, KBL-H and SKL/KBL-LP, we'd check 4 ports more then we have, but that doesn't hurt -- To view, visit https://review.coreboot.org/c/coreboot/+/52627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5155356bd302ef938c76eb60688276fec67502 Gerrit-Change-Number: 52627 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 22:44:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2021