coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/skylake: Allow to use Amber Lake FSP
by Felix Singer (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Timofey Komarov, Nico Huber, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Allow to use Amber Lake FSP ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52692/comment/197f1816_9546cb4b PS5, Line 7: to use using -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 5 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 30 Apr 2021 02:38:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] soc/intel/skylake: Introduce new method for setting device states
by Felix Singer (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Raul Rangel, Nico Huber, Furquan Shaikh, Matt DeVillier, Angel Pons, Patrick Rudolph, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] soc/intel/skylake: Introduce new method for setting device states ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/skylake/fspdevmap.h: https://review.coreboot.org/c/coreboot/+/52493/comment/66b6f7af_70b44ba5 PS9, Line 9: const uint8_t inverted; > This seems like this is an optional field. […] Actually, I have thought about this but decided against doing it, because IMO it would make the listing look a bit more messy since the FSP option names might differ in their name length a lot, which makes it less readable. So I put everything else before the UPD option. But that's just me. Other opinions? -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Apr 2021 02:26:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Felix Singer (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Furquan Shaikh, Selma Bensaid, Paul Menzel, Meera Ravindranath, Angel Pons, Subrata Banik, Ronak Kanabar, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51849/comment/48a63b9c_70b1b1e1 PS11, Line 7: Enable VT-d The code gives the opportunity for VT-d configuration. Rather write something like: Hook up FSP UPDs for VT-d configuration https://review.coreboot.org/c/coreboot/+/51849/comment/aeb20fec_f1ec65b7 PS11, Line 9: enabling configuring -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 11 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 30 Apr 2021 02:11:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/dram: Add support for LPDDR4 4266
by build bot (Jenkins) (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Marshall Dawson, Nikolai Vyssotski, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52745 ) Change subject: device/dram: Add support for LPDDR4 4266 ...................................................................... Patch Set 3: (2 comments) File src/device/dram/ddr4.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118080): https://review.coreboot.org/c/coreboot/+/52745/comment/2d2f8d26_a4275cec PS3, Line 172: return (speed_mhz_to_reported_mts(speed_mhz, ddr4_speeds, ARRAY_SIZE(ddr4_speeds))); return is not a function, parentheses are not required Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118080): https://review.coreboot.org/c/coreboot/+/52745/comment/a071e8f2_1fac4d81 PS3, Line 180: return(speed_mhz_to_reported_mts(speed_mhz, lpddr4_speeds, ARRAY_SIZE(lpddr4_speeds))); return is not a function, parentheses are not required -- To view, visit https://review.coreboot.org/c/coreboot/+/52745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Gerrit-Change-Number: 52745 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Apr 2021 01:21:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/dram: Add support for LPDDR4 4266
by Nikolai Vyssotski (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Marshall Dawson, Nikolai Vyssotski, Felix Held. Hello build bot (Jenkins), Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52745 to look at the new patch set (#3). Change subject: device/dram: Add support for LPDDR4 4266 ...................................................................... device/dram: Add support for LPDDR4 4266 Add 4266 MT/s LPDDD4 to a separate lpddr4_speed table. Set min/max limits to 1866/2133 MHz per JEDEC 209-4C. BUG=b:184124605 Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/device/dram/ddr4.c M src/include/device/dram/ddr4.h 2 files changed, 42 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/52745/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Gerrit-Change-Number: 52745 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by David Hendricks (Code Review) 30 Apr '21

30 Apr '21

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49286 ) Change subject: src/acpi: Add APEI EINJ support ...................................................................... src/acpi: Add APEI EINJ support This adds full EINJ support with trigger action tables. The actual error injection functionality is HW specific. Therefore, HW specific code should call acpi_create_einj with an address where action table resides. The default params of the action table are filled out by the common code. Control is then returned back to the caller to modify or override default parameters. If no changes are needed, caller can simply add the acpi table. At runtime, FW is responsible for filling out the action table with the proper entries. The action table memory is shared between FW and OS. This memory should be marked as reserved in E820 table. Tested on Deltalake mainboard. Boot to OS, load the EINJ driver ( modprobe EINJ) and verify EINJ memory entries are in /proc/iomem. Further tested by injecting errors via the APEI file nodes. More information on error injection can be referenced in the latest ACPI spec. Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Rocky Phagura --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h 3 files changed, 283 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Rocky Phagura: Looks good to me, but someone else must approve diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 11e703c..9ffd7a9 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -38,6 +38,12 @@ help Selected by platforms that don't expose a PC/AT 8259 PIC pair. +config ACPI_EINJ + def_bool n + depends on HAVE_ACPI_TABLES + help + This variable provides control for ACPI error injection table (EINJ) + config HAVE_ACPI_TABLES bool help diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 64af505..5c3fe13 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -785,6 +785,152 @@ header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +/* + * This method adds the ACPI error injection capability. It fills the default information. + * HW dependent code (caller) can modify the defaults upon return. If no changes are necessary + * and the defaults are acceptable then caller can simply add the table (acpi_add_table). + * INPUTS: + * einj - ptr to the starting location of EINJ table + * actions - number of actions to trigger an error (HW dependent) + * addr - address of trigger action table. This should be ACPI reserved memory and it will be + * shared between OS and FW. + */ +void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions) +{ + int i; + acpi_header_t *header = &(einj->header); + acpi_injection_header_t *inj_header = &(einj->inj_header); + acpi_einj_smi_t *einj_smi = (acpi_einj_smi_t *)addr; + acpi_einj_trigger_table_t *tat; + if (!header) + return; + + printk(BIOS_DEBUG, "%s einj_smi = %p\n", __func__, einj_smi); + memset(einj_smi, 0, sizeof(acpi_einj_smi_t)); + tat = (acpi_einj_trigger_table_t *)(einj_smi + sizeof(acpi_einj_smi_t)); + tat->header_size = 16; + tat->revision = 0; + tat->table_size = sizeof(acpi_einj_trigger_table_t) + + sizeof(acpi_einj_action_table_t) * actions - 1; + tat->entry_count = actions; + printk(BIOS_DEBUG, "%s trigger_action_table = %p\n", __func__, tat); + + for (i = 0; i < actions; i++) { + tat->trigger_action[i].action = TRIGGER_ERROR; + tat->trigger_action[i].instruction = NO_OP; + tat->trigger_action[i].flags = FLAG_IGNORE; + tat->trigger_action[i].reg.space_id = ACPI_ADDRESS_SPACE_MEMORY; + tat->trigger_action[i].reg.bit_width = 64; + tat->trigger_action[i].reg.bit_offset = 0; + tat->trigger_action[i].reg.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS; + tat->trigger_action[i].reg.addr = 0; + tat->trigger_action[i].value = 0; + tat->trigger_action[i].mask = 0xFFFFFFFF; + } + + acpi_einj_action_table_t default_actions[ACTION_COUNT] = { + [0] = { + .action = BEGIN_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), + .value = 0, + .mask = 0xFFFFFFFF + }, + [1] = { + .action = GET_TRIGGER_ACTION_TABLE, + .instruction = READ_REGISTER, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->trigger_action_table), + .value = 0, + .mask = 0xFFFFFFFFFFFFFFFF + }, + [2] = { + .action = SET_ERROR_TYPE, + .instruction = WRITE_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inject[0]), + .value = 0, + .mask = 0xFFFFFFFF + }, + [3] = { + .action = GET_ERROR_TYPE, + .instruction = READ_REGISTER, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inj_cap), + .value = 0, + .mask = 0xFFFFFFFF + }, + [4] = { + .action = END_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), + .value = 0, + .mask = 0xFFFFFFFF + + }, + [5] = { + .action = EXECUTE_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_IO(), + .value = 0x9a, + .mask = 0xFFFF, + }, + [6] = { + .action = CHECK_BUSY_STATUS, + .instruction = READ_REGISTER_VALUE, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_status), + .value = 1, + .mask = 1, + }, + [7] = { + .action = GET_CMD_STATUS, + .instruction = READ_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->cmd_sts), + .value = 0, + .mask = 0x1fe, + }, + [8] = { + .action = SET_ERROR_TYPE_WITH_ADDRESS, + .instruction = WRITE_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->setaddrtable), + .value = 1, + .mask = 0xffffffff + } + }; + + einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP; + einj_smi->trigger_action_table = (u64) (uintptr_t)tat; + + for (i = 0; i < ACTION_COUNT; i++) + printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i, + default_actions[i].reg.addr); + + memset((void *)einj, 0, sizeof(einj)); + + /* Fill out header fields. */ + memcpy(header->signature, "EINJ", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(acpi_einj_t); + header->revision = 1; + inj_header->einj_header_size = sizeof(acpi_injection_header_t); + inj_header->entry_count = ACTION_COUNT; + + printk(BIOS_DEBUG, "%s einj->action_table = %p\n", + __func__, einj->action_table); + memcpy((void *)einj->action_table, (void *)default_actions, sizeof(einj->action_table)); + header->checksum = acpi_checksum((void *)einj, sizeof(einj)); +} + void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(const struct device *device, @@ -1756,6 +1902,8 @@ return 1; case RSDP: /* ACPI 2.0 upto 6.3: 2 */ return 2; + case EINJ: + return 1; case HEST: return 1; case NHLT: diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index f2d2ad9..b266acf 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -71,7 +71,7 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ - BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, + BERT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT @@ -980,6 +980,134 @@ u8 reserved3; } __packed; +/* EINJ APEI Standard Definitions */ +/* EINJ Error Types + Refer to the ACPI spec, EINJ section, for more info on bit definitions +*/ +#define ACPI_EINJ_CPU_CE (1 << 0) +#define ACPI_EINJ_CPU_UCE (1 << 1) +#define ACPI_EINJ_CPU_UCE_FATAL (1 << 2) +#define ACPI_EINJ_MEM_CE (1 << 3) +#define ACPI_EINJ_MEM_UCE (1 << 4) +#define ACPI_EINJ_MEM_UCE_FATAL (1 << 5) +#define ACPI_EINJ_PCIE_CE (1 << 6) +#define ACPI_EINJ_PCIE_UCE_NON_FATAL (1 << 7) +#define ACPI_EINJ_PCIE_UCE_FATAL (1 << 8) +#define ACPI_EINJ_PLATFORM_CE (1 << 9) +#define ACPI_EINJ_PLATFORM_UCE (1 << 10) +#define ACPI_EINJ_PLATFORM_UCE_FATAL (1 << 11) +#define ACPI_EINJ_VENDOR_DEFINED (1 << 31) +#define ACPI_EINJ_DEFAULT_CAP (ACPI_EINJ_MEM_CE | ACPI_EINJ_MEM_UCE | \ + ACPI_EINJ_PCIE_CE | ACPI_EINJ_PCIE_UCE_FATAL) + +/* EINJ actions */ +#define ACTION_COUNT 9 +#define BEGIN_INJECT_OP 0x00 +#define GET_TRIGGER_ACTION_TABLE 0x01 +#define SET_ERROR_TYPE 0x02 +#define GET_ERROR_TYPE 0x03 +#define END_INJECT_OP 0x04 +#define EXECUTE_INJECT_OP 0x05 +#define CHECK_BUSY_STATUS 0x06 +#define GET_CMD_STATUS 0x07 +#define SET_ERROR_TYPE_WITH_ADDRESS 0x08 +#define TRIGGER_ERROR 0xFF + +/* EINJ Instructions */ +#define READ_REGISTER 0x00 +#define READ_REGISTER_VALUE 0x01 +#define WRITE_REGISTER 0x02 +#define WRITE_REGISTER_VALUE 0x03 +#define NO_OP 0x04 + +/* EINJ (Error Injection Table) */ +typedef struct acpi_gen_regaddr1 { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size since ACPI 2.0c */ + u64 addr; /* Register address */ +} __packed acpi_addr64_t; + +/* Instruction entry */ +typedef struct acpi_einj_action_table { + u8 action; + u8 instruction; + u16 flags; + acpi_addr64_t reg; + u64 value; + u64 mask; +} __packed acpi_einj_action_table_t; + +typedef struct acpi_injection_header { + u32 einj_header_size; + u32 flags; + u32 entry_count; +} __packed acpi_injection_header_t; + +typedef struct acpi_einj_trigger_table { + u32 header_size; + u32 revision; + u32 table_size; + u32 entry_count; + acpi_einj_action_table_t trigger_action[1]; +} __packed acpi_einj_trigger_table_t; + +typedef struct set_error_type { + u32 errtype; + u32 vendorerrortype; + u32 flags; + u32 apicid; + u64 memaddr; + u64 memrange; + u32 pciesbdf; +} __packed set_error_type_t; + +#define EINJ_PARAM_NUM 6 +typedef struct acpi_einj_smi { + u64 op_state; + u64 err_inject[EINJ_PARAM_NUM]; + u64 trigger_action_table; + u64 err_inj_cap; + u64 op_status; + u64 cmd_sts; + u64 einj_addr; + u64 einj_addr_msk; + set_error_type_t setaddrtable; + u64 reserved[50]; +} __packed acpi_einj_smi_t; + +/* EINJ Flags */ +#define EINJ_DEF_TRIGGER_PORT 0xb2 +#define FLAG_PRESERVE 0x01 +#define FLAG_IGNORE 0x00 + +/* EINJ Registers */ +#define EINJ_REG_MEMORY(address) \ + { \ + .space_id = ACPI_ADDRESS_SPACE_MEMORY, \ + .bit_width = 64, \ + .bit_offset = 0, \ + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \ + .addr = address} + +#define EINJ_REG_IO() \ + { \ + .space_id = ACPI_ADDRESS_SPACE_IO, \ + .bit_width = 0x10, \ + .bit_offset = 0, \ + .access_size = ACPI_ACCESS_SIZE_WORD_ACCESS, \ + .addr = EINJ_DEF_TRIGGER_PORT} /* HW dependent code can override this also */ + +typedef struct acpi_einj { + acpi_header_t header; + acpi_injection_header_t inj_header; + acpi_einj_action_table_t action_table[ACTION_COUNT]; +} __packed acpi_einj_t; + + +void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); + unsigned long fw_cfg_acpi_tables(unsigned long start); /* These are implemented by the target port or north/southbridge. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 14 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Add Thermal Zone support
by Raul Rangel (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Marshall Dawson, Rob Barnes. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52772 ) Change subject: mb/google/guybrush: Add Thermal Zone support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52772/comment/6ef883a1_be718261 PS1, Line 9: he file thermal.asl is a : direct copy with the exception of remo Can we move it to common and include it in cezanne/soc.asl? -- To view, visit https://review.coreboot.org/c/coreboot/+/52772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe0b7ed23f108e42abf7a9b13580b974fd61ec1 Gerrit-Change-Number: 52772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Fri, 30 Apr 2021 01:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by Rocky Phagura (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Lance Zhao, Marc Jones, Furquan Shaikh, Duncan Laurie, David Hendricks, Angel Pons. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49286 ) Change subject: src/acpi: Add APEI EINJ support ...................................................................... Patch Set 13: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49286/comment/299f0b09_10ca204e PS2, Line 14: memeory > memory fixed. https://review.coreboot.org/c/coreboot/+/49286/comment/ea767206_5dc16b87 PS2, Line 19: errors via the APEI file nodes. More information on error injection is here. > check your line length in the commit message so you don't get the strange wrapping here. fixed Patchset: PS13: All comments resolved. File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49286/comment/b00ef524_b7c0a659 PS2, Line 805: acpi_einj_action_table_t default_actions[] = { : /* Action 0 */ : { : .action = BEGIN_INJECT_OP, : .instruction = WRITE_REGISTER_VALUE, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_MEMORY(), : .value = 0, : .mask = 0xFFFFFFFF : }, : /* Action 1 */ : { : .action = GET_TRIGGER_ACTION_TABLE, : .instruction = READ_REGISTER, : .flags = FLAG_IGNORE, : .reg = EINJ_REG_MEMORY(), : .value = 0x0, : .mask = 0xFFFFFFFFFFFFFFFF : }, : /* Action 2 */ : { : .action = SET_ERROR_TYPE, : .instruction = WRITE_REGISTER, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_MEMORY(), : .value = 0x0, : .mask = 0xFFFFFFFF : }, : /* Action 3 */ : { : .action = GET_ERROR_TYPE, : .instruction = READ_REGISTER, : .flags = FLAG_IGNORE, : .reg = EINJ_REG_MEMORY(), : .value = 0x0, : .mask = 0xFFFFFFFF : }, : /* Action 4 */ : { : .action = END_INJECT_OP, : .instruction = WRITE_REGISTER_VALUE, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_MEMORY(), : .value = 0x0, : .mask = 0xFFFFFFFF : }, : /* Action 5 */ : { : .action = EXECUTE_INJECT_OP, : .instruction = WRITE_REGISTER_VALUE, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_IO(), : .value = 0x9a, : .mask = 0xFFFF : }, : /* Action 6 */ : { : .action = CHECK_BUSY_STATUS, : .instruction = READ_REGISTER_VALUE, : .flags = FLAG_IGNORE, : .reg = EINJ_REG_MEMORY(), : .value = 0x1, : .mask = 0x1 : }, : /* Action 7 */ : { : .action = GET_CMD_STATUS, : .instruction = READ_REGISTER, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_MEMORY(), : .value = 0x0, : .mask = 0x1fe : }, : /* Action 8 */ : { : .action = SET_ERROT_TYPE_WITH_ADDRESS, : .instruction = WRITE_REGISTER, : .flags = FLAG_PRESERVE, : .reg = EINJ_REG_MEMORY(), : .value = 0x1, : .mask = 0xffffffff : } : }; > action count could be sizeof default_actions here. […] Fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 13 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Apr 2021 01:08:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by Rocky Phagura (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Marc Jones, Furquan Shaikh, Duncan Laurie, David Hendricks, Angel Pons. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49286 ) Change subject: src/acpi: Add APEI EINJ support ...................................................................... Patch Set 12: Code-Review+1 (1 comment) Patchset: PS12: David, This is ready to be merged. Thank you for the review everybody! -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 12 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Attention: David Hendricks Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Apr 2021 00:57:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add Thermal Zone support
by Marshall Dawson (Code Review) 30 Apr '21

30 Apr '21

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52772 ) Change subject: mb/google/guybrush: Add Thermal Zone support ...................................................................... mb/google/guybrush: Add Thermal Zone support Duplicate the functionality from Zork. The file thermal.asl is a direct copy with the exception of removing an extra blank like and declaring PPKG as External. BUG=b:186166365 TEST=Build Guybrush Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ifbe0b7ed23f108e42abf7a9b13580b974fd61ec1 --- M src/mainboard/google/guybrush/dsdt.asl A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h A src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl A src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h 5 files changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52772/1 diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl index 9579ae3..2e8f609 100644 --- a/src/mainboard/google/guybrush/dsdt.asl +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -23,4 +23,6 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + /* Thermal handler */ + #include <variant/acpi/thermal.asl> } diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl new file mode 100644 index 0000000..f3900cc --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Generated by acpigen */ +External (\PPKG, MethodObj) + +#include <variant/thermal.h> + +/* Thermal Zone */ + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + /* Thermal constants for passive cooling */ + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 2 seconds */ + Name (_TSP, 20) + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Local0 = Arg0 * 10 + + /* Convert to Kelvin */ + Local0 += 2732 + + Return (Local0) + } + + /* Threshold for OS to shutdown */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Threshold for passive cooling */ + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + /* Processors used for passive cooling */ + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + /* Get temperature from EC in deci-kelvin */ + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) + + /* Critical temperature in deci-kelvin */ + Local1 = CTOK (\TCRT) + + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 + + /* Wait 1 second for EC to re-poll */ + Sleep (1000) + + /* Re-read temperature from EC */ + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) + + Debug = "RE-READ TEMPERATURE" + Debug = Local0 + } + + Return (Local0) + } + } +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h new file mode 100644 index 0000000..b3c951b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Picasso Thermal Requirements + * TDP (W) 15 + * T die,max (°C) 105 + * T ctl,max 105 + * T die,lmt (default) 100 + * T ctl,lmt (default) 100 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +#endif diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl b/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..7a793d8 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h b/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h new file mode 100644 index 0000000..2af6479 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/52772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe0b7ed23f108e42abf7a9b13580b974fd61ec1 Gerrit-Change-Number: 52772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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