coreboot-gerrit April 2021

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Change in coreboot[master]: [RFC] device/pnp: do not warn for generic unassigned ressources
by Michael Niewöhner (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48934 ) Change subject: [RFC] device/pnp: do not warn for generic unassigned ressources ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic23852d525a3f9c95118b113d419f815cac002d3 Gerrit-Change-Number: 48934 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 21:34:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/rt8168: support loading MAC address from vpd.bin
by Matt DeVillier (Code Review) 30 Apr '21

30 Apr '21

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30231 ) Change subject: drivers/net/rt8168: support loading MAC address from vpd.bin ...................................................................... Abandoned no longer needed since using RO_VPD FMAP region -- To view, visit https://review.coreboot.org/c/coreboot/+/30231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If18ab2cd0148c1272cbe65c2ad8864ddd3b4ddf8 Gerrit-Change-Number: 30231 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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Change in coreboot[master]: Final line update, take 2
by Star Labs (Code Review) 30 Apr '21

30 Apr '21

Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52770 ) Change subject: Final line update, take 2 ...................................................................... Final line update, take 2 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I62f395833947cc3ddc1570ea5c92da0b0c080444 --- M src/ec/starlabs/it8987/acpi/thermal.asl M src/mainboard/starlabs/labtop/acpi/mainboard.asl M src/mainboard/starlabs/labtop/spd/Makefile.inc M src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52770/1 diff --git a/src/ec/starlabs/it8987/acpi/thermal.asl b/src/ec/starlabs/it8987/acpi/thermal.asl index bd85543..6bf25bf 100644 --- a/src/ec/starlabs/it8987/acpi/thermal.asl +++ b/src/ec/starlabs/it8987/acpi/thermal.asl @@ -12,4 +12,3 @@ } } } - diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl index 2d79f52..7b955c4 100644 --- a/src/mainboard/starlabs/labtop/acpi/mainboard.asl +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -55,4 +55,3 @@ #define EC_GPE_SCI 0x50 /* GPP_E16 */ #include <ec/starlabs/it8987/acpi/ec.asl> - diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc index 3be9ad5..9e7f4e3 100644 --- a/src/mainboard/starlabs/labtop/spd/Makefile.inc +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -19,4 +19,3 @@ SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h index f26e256..d432b51 100644 --- a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h @@ -188,4 +188,3 @@ #endif #endif - -- To view, visit https://review.coreboot.org/c/coreboot/+/52770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62f395833947cc3ddc1570ea5c92da0b0c080444 Gerrit-Change-Number: 52770 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: Fixed final new lines
by Star Labs (Code Review) 30 Apr '21

30 Apr '21

Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52769 ) Change subject: Fixed final new lines ...................................................................... Fixed final new lines Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Id9e077346c474d3a89978bd3970ff6f12e239eb7 --- M src/ec/starlabs/it8987/Makefile.inc M src/ec/starlabs/it8987/acpi/thermal.asl M src/mainboard/starlabs/labtop/acpi/mainboard.asl M src/mainboard/starlabs/labtop/hda_verb.c M src/mainboard/starlabs/labtop/spd/Makefile.inc M src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h M src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h M src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h 8 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52769/1 diff --git a/src/ec/starlabs/it8987/Makefile.inc b/src/ec/starlabs/it8987/Makefile.inc index 10c9dcd..b021d0f 100644 --- a/src/ec/starlabs/it8987/Makefile.inc +++ b/src/ec/starlabs/it8987/Makefile.inc @@ -24,4 +24,3 @@ printf "coreboot has been built without the IT8987 EC Firmware.\n" printf "Do not flash this image. Your LabTop Mk IV's power button\n" printf "may not respond when you press it.\n\n" - diff --git a/src/ec/starlabs/it8987/acpi/thermal.asl b/src/ec/starlabs/it8987/acpi/thermal.asl index 983a6d9..bd85543 100644 --- a/src/ec/starlabs/it8987/acpi/thermal.asl +++ b/src/ec/starlabs/it8987/acpi/thermal.asl @@ -11,4 +11,5 @@ Notify (\_TZ.TZ01, 0x80) } } -} \ No newline at end of file +} + diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl index 9666055..2d79f52 100644 --- a/src/mainboard/starlabs/labtop/acpi/mainboard.asl +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -56,4 +56,3 @@ #include <ec/starlabs/it8987/acpi/ec.asl> - diff --git a/src/mainboard/starlabs/labtop/hda_verb.c b/src/mainboard/starlabs/labtop/hda_verb.c index 34bb4af..c260297 100644 --- a/src/mainboard/starlabs/labtop/hda_verb.c +++ b/src/mainboard/starlabs/labtop/hda_verb.c @@ -1,4 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "variant/hda_verb.h" - diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc index ca39059..3be9ad5 100644 --- a/src/mainboard/starlabs/labtop/spd/Makefile.inc +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -18,4 +18,5 @@ SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0110 SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) \ No newline at end of file +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h index 05af1d3..f26e256 100644 --- a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h @@ -189,4 +189,3 @@ #endif - diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h index f60a51f..2ad9096 100644 --- a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h @@ -75,4 +75,3 @@ AZALIA_ARRAY_SIZES; #endif - diff --git a/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h index 0e86541..3e9d5aa 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h +++ b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h @@ -172,4 +172,3 @@ AZALIA_ARRAY_SIZES; #endif - -- To view, visit https://review.coreboot.org/c/coreboot/+/52769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9e077346c474d3a89978bd3970ff6f12e239eb7 Gerrit-Change-Number: 52769 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: Updated mainboard.c
by Star Labs (Code Review) 30 Apr '21

30 Apr '21

Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52768 ) Change subject: Updated mainboard.c ...................................................................... Updated mainboard.c Change-Id: I26c9861e3c4335d8819e0925b1e0f9532a4bb6fb --- M src/ec/starlabs/it8987/acpi/ac.asl M src/ec/starlabs/it8987/acpi/cmos.asl M src/ec/starlabs/it8987/acpi/ec.asl M src/ec/starlabs/it8987/acpi/hid.asl M src/ec/starlabs/it8987/acpi/keyboard.asl M src/mainboard/starlabs/labtop/acpi/mainboard.asl M src/mainboard/starlabs/labtop/mainboard.c 7 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52768/1 diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl index 860bc86..97ae147 100644 --- a/src/ec/starlabs/it8987/acpi/ac.asl +++ b/src/ec/starlabs/it8987/acpi/ac.asl @@ -50,7 +50,7 @@ Notify (ADP1, 0x80) } -Method(_Q0B, 0, NotSerialized) // Battery Connected +Method(_Q0B, 0, NotSerialized) // Battery Connected { // 500ms delay - Not used in coreboot // Sleep (500) diff --git a/src/ec/starlabs/it8987/acpi/cmos.asl b/src/ec/starlabs/it8987/acpi/cmos.asl index 3368473..052094c 100644 --- a/src/ec/starlabs/it8987/acpi/cmos.asl +++ b/src/ec/starlabs/it8987/acpi/cmos.asl @@ -3,7 +3,7 @@ OperationRegion (CMOS, SystemIO, 0x70, 0x02) Field (CMOS, ByteAcc, NoLock, Preserve) { - NVRI, 8, + NVRI, 8, NVRD, 8 } diff --git a/src/ec/starlabs/it8987/acpi/ec.asl b/src/ec/starlabs/it8987/acpi/ec.asl index 1efe309..2628cd5 100644 --- a/src/ec/starlabs/it8987/acpi/ec.asl +++ b/src/ec/starlabs/it8987/acpi/ec.asl @@ -30,7 +30,7 @@ // Include the definitions for accessing CMOS. #include "cmos.asl" - // Our embedded controller device. + // Our embedded controller device. Device (H_EC) { Name (_HID, EISAID ("PNP0C09")) // ACPI Embedded Controller @@ -46,7 +46,7 @@ Name(ECON, 1) // AC debug Name(BNUM, 0) // Number Of Batteries Present - Name(PVOL, ASL_PVOL_DEFOF_NUM) + Name(PVOL, ASL_PVOL_DEFOF_NUM) Name(B1CC, 0) Name(B2CC, 0) @@ -79,7 +79,7 @@ Name(PB10, 0) Name(IWCW, 0) Name(IWCR, 0) - Name(BTEN, 0) + Name(BTEN, 0) Mutex(ECMT, 0) Method (_CRS, 0, Serialized) @@ -110,19 +110,19 @@ { ECOS = 1 ECAV = 1 - + // Unconditionally fix up the Battery and Power State. - + // Initialize the Number of Present Batteries. // 1 = Real Battery 1 is present // 2 = Real Battery 2 is present // 3 = Real Battery 1 and 2 are present BNUM = 0 BNUM |= ((ECRD (RefOf (ECWR)) & 0x02) >> 1) - + // Save the current Power State for later. // Store (PWRS, Local0) - + // Initialize the Power State. // BNUM = 0 = Virtual Power State // BNUM > 0 = Real Power State @@ -177,14 +177,14 @@ XXX1, 8, // EC Firmware sub- version number. XXX2, 8, // EC Firmware test- version number. - Offset(0x06), + Offset(0x06), SKID, 8, // SKU ID Offset(0x11), KBCD, 8, // Key / Touch Pad disable/enable bit ECOS, 8, // Enter OS flag HDAO, 8, - ECHK, 8, // Hot keys flag + ECHK, 8, // Hot keys flag Offset(0x18), KLBS, 8, // Keyboard backlight begin. @@ -195,7 +195,7 @@ PWPF, 8, // Power Profile Offset(0x1E), - BTHP,8, // Health Battery Percentage + BTHP,8, // Health Battery Percentage Offset(0x20), RCMD, 8, // Same function as IO 66 port to send EC command @@ -205,9 +205,9 @@ FNST, 8, // FN LOCK key status. Offset(0x3F), - SFAN, 8, // Set Fan Speed. - BTMP, 16, // Battery Temperature. - BCNT, 16, // Battery Cycle Count. + SFAN, 8, // Set Fan Speed. + BTMP, 16, // Battery Temperature. + BCNT, 16, // Battery Cycle Count. FRMP, 16, // Fan Current Speed. Offset(0x60), @@ -237,16 +237,16 @@ CHGR, 16, // Charge Rate Offset(0x70), - CPTM, 8, // CPU Temperature + CPTM, 8, // CPU Temperature - Offset(0x72), - TER2, 8, // Charger Temperature, Charger thermistor support + Offset(0x72), + TER2, 8, // Charger Temperature, Charger thermistor support Offset(0x7F), LSTE, 1, // Lid feature // BIT0LID GPI , 7, // Reserved - + Offset(0x80), ECWR, 8, // AC & Battery status XX10, 8, // Battery#1 Model Number Code @@ -275,7 +275,7 @@ MGI9, 8, MGIA, 8, MGIB, 8, - MGIC, 8, + MGIC, 8, MGID, 8, MGIE, 8, MGIF, 8, @@ -319,7 +319,7 @@ CTL5, 8, CTL6, 8, CTL7, 8, - + Offset(0xF0), , 3,// BIT0 .. BIT2 Reserved TPCC, 1,// BIT3 TypeC connection bit diff --git a/src/ec/starlabs/it8987/acpi/hid.asl b/src/ec/starlabs/it8987/acpi/hid.asl index b0e71da..cc6bce6 100644 --- a/src/ec/starlabs/it8987/acpi/hid.asl +++ b/src/ec/starlabs/it8987/acpi/hid.asl @@ -29,9 +29,9 @@ Store ("-----> HDDM", Debug) Name (DPKG, Package (0x04) { - 0x11111111, - 0x22222222, - 0x33333333, + 0x11111111, + 0x22222222, + 0x33333333, 0x44444444 }) Return (DPKG) diff --git a/src/ec/starlabs/it8987/acpi/keyboard.asl b/src/ec/starlabs/it8987/acpi/keyboard.asl index fd7ab97..f5b1d52 100644 --- a/src/ec/starlabs/it8987/acpi/keyboard.asl +++ b/src/ec/starlabs/it8987/acpi/keyboard.asl @@ -14,24 +14,24 @@ Notify (\_SB.HIDD, 0xC6) Notify (\_SB.HIDD, 0xC7) Store ("<----- _Q81", Debug) -} +} Method(_Q99) // Wireless mode { Store ("-----> _Q99", Debug) - \_SB.HIDD.HPEM(8) + \_SB.HIDD.HPEM(8) Store ("<----- _Q80", Debug) } Method(_Q06) // Brightness decrease { \_SB.PCI0.GFX0.DECB() -} +} Method(_Q07) // Brightness increase { \_SB.PCI0.GFX0.INCB() -} +} Method(_Q08) // FN lock QEvent { diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl index bf73244..9666055 100644 --- a/src/mainboard/starlabs/labtop/acpi/mainboard.asl +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -34,7 +34,7 @@ Name (_CID, Package (0x02) { - "PRP00001", + "PRP00001", "PNP0A05" }) @@ -45,7 +45,7 @@ } } -/* +/* * ITE IT8987E Embedded Controller * * We include this here as we need to support different levels within diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index b0073c7..71d96e6 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -9,7 +9,7 @@ /* Override the BIOS version using smbios_mainboard_bios_version() */ const char *smbios_mainboard_bios_version(void) { -#if CONFIG_BOARD_STARLABS_STARBOOK_TGL +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) return "CB_0"; #else return "CB_5"; @@ -34,9 +34,9 @@ /* Override smbios_system_sku */ const char *smbios_system_sku(void) { -#if CONFIG_BOARD_STARLABS_STARBOOK_TGL +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) return "B5"; -#elif CONFIG_BOARD_STARLABS_LABTOP_CML +#elif CONFIG(BOARD_STARLABS_LABTOP_CML) return "L4"; #else return "L3-U"; -- To view, visit https://review.coreboot.org/c/coreboot/+/52768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c9861e3c4335d8819e0925b1e0f9532a4bb6fb Gerrit-Change-Number: 52768 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Add temporary _AIE table
by build bot (Jenkins) (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Raul Rangel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52766 ) Change subject: mb/google/guybrush: Add temporary _AIE table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118067): https://review.coreboot.org/c/coreboot/+/52766/comment/ef8b7113_63f7d10f PS2, Line 61: #define EC_ENABLE_WAKE_PIN Package() {\_SB.GPIO, 0} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/52766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8508e5fd8f23a6a8364a8dbf919568d472cc9409 Gerrit-Change-Number: 52766 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 20:43:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add temporary _AIE table
by Raul Rangel (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52766 to look at the new patch set (#2). Change subject: mb/google/guybrush: Add temporary _AIE table ...................................................................... mb/google/guybrush: Add temporary _AIE table On Cezanne, S0i3 wakes are all handled by the GPIO controller. When a wake is asserted, the GPIO controller is the only subsystem that registers the wake. There are no GEVENTs/GPEs raised. This means that we can't use the GPE number in the _PRW package for two reasons: 1) The GPE will never get asserted, so the device will not be credited as being the wake source. 2) The GPIO's wake_status bit will never get cleared. This means that on a second S0i3 sleep, the system will be instantly woken up. In order to solve these problems, we need to tell the OS which GPIOs can be used to wake up the system. By providing the _AEI table we give the OS the ability to * Enable/disable if a GPIO is a wake source. This doesn't technically work yet because the GPIO kernel driver had not yet implemented irq_set_wake. * Associate a GPIO wake with a device so it can correctly increment the wake_source. * Clear the wake_status bit from the GPIO. This CL is currently a workaround. Coreboot doesn't yet have any infrastructure for generating the _AEI table. The ACPI chip drivers (drivers/i2c/generic, drivers/uart/acpi, etc) don't have the ability to specify the _AEI index as a wake source either. This will all be implemented in later CLs. This CL only handles EC_SOC_WAKE_ODL. It allows testing S0i3 resume using the internal keyboard, and the lid switch. Other devices will need to be added as they are tested. BUG=b:185621145 TEST=Multiple S0i3 cycles using internal keyboard Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I8508e5fd8f23a6a8364a8dbf919568d472cc9409 --- A src/mainboard/google/guybrush/aei.asl M src/mainboard/google/guybrush/dsdt.asl M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 3 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52766/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8508e5fd8f23a6a8364a8dbf919568d472cc9409 Gerrit-Change-Number: 52766 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Added LabTop series Added ITE 8987E Added LOCKDIS to mark SPI as writ...
by build bot (Jenkins) (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52767 ) Change subject: Added LabTop series Added ITE 8987E Added LOCKDIS to mark SPI as writable in SKL Added CMOS setting to disable ME ...................................................................... Patch Set 1: (128 comments) File src/ec/starlabs/it8987/acpi/ac.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/a95de97d_ea3f8d79 PS1, Line 53: Method(_Q0B, 0, NotSerialized) // Battery Connected trailing whitespace File src/ec/starlabs/it8987/acpi/cmos.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/94ce2139_bb224861 PS1, Line 6: NVRI, 8, trailing whitespace File src/ec/starlabs/it8987/acpi/ec.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3e7d276a_0777206e PS1, Line 33: // Our embedded controller device. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/18388fa4_81e48f1c PS1, Line 49: Name(PVOL, ASL_PVOL_DEFOF_NUM) trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/1058449a_ff0b954d PS1, Line 82: Name(BTEN, 0) trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6b7c72e0_6cc58f3c PS1, Line 113: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/9a08b918_6225e0c7 PS1, Line 115: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/fd121e99_a1a6612f PS1, Line 122: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/8609716b_2a8aedcb PS1, Line 125: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/67f3156b_5768d759 PS1, Line 180: Offset(0x06), trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/d39915dd_71b0ef4b PS1, Line 187: ECHK, 8, // Hot keys flag trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/15787c9c_8ed397a1 PS1, Line 198: BTHP,8, // Health Battery Percentage trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/1edca52a_247468d9 PS1, Line 208: SFAN, 8, // Set Fan Speed. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/5b1494b1_4694981c PS1, Line 209: BTMP, 16, // Battery Temperature. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/77f0657d_cd510eec PS1, Line 210: BCNT, 16, // Battery Cycle Count. trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6e4375bb_d996d195 PS1, Line 240: CPTM, 8, // CPU Temperature trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/2b587801_df7a8787 PS1, Line 242: Offset(0x72), trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/0a4c5485_0bc32cc5 PS1, Line 243: TER2, 8, // Charger Temperature, Charger thermistor support trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/dd1fc24e_2b007afd PS1, Line 249: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/a4b2b9dd_518ea486 PS1, Line 278: MGIC, 8, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/eab46b0e_aed10853 PS1, Line 322: trailing whitespace File src/ec/starlabs/it8987/acpi/hid.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/845bf25d_d7a111b3 PS1, Line 32: 0x11111111, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/04deb7dc_71699b7a PS1, Line 33: 0x22222222, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6b8bd933_790a2f6f PS1, Line 34: 0x33333333, trailing whitespace File src/ec/starlabs/it8987/acpi/keyboard.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3e147a70_cd56de12 PS1, Line 17: } trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/a2725be2_efc0fc34 PS1, Line 22: \_SB.HIDD.HPEM(8) trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bea3a212_3d406e08 PS1, Line 29: } trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/beed2af4_0eff1261 PS1, Line 34: } trailing whitespace File src/mainboard/starlabs/labtop/acpi/mainboard.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/146e6f0c_6d52cc2b PS1, Line 37: "PRP00001", trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/a94ad7f7_a6bf5936 PS1, Line 48: /* trailing whitespace File src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4e8064b8_c652e62b PS1, Line 18: _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ea2364b9_56ff13b8 PS1, Line 19: _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/198193c8_eecf2ba4 PS1, Line 22: _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/50101308_08f9c268 PS1, Line 23: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/1f4ccf16_00084f0e PS1, Line 35: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/422e9f24_c6528f6f PS1, Line 36: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/fdc1c863_0761640c PS1, Line 37: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bfceacbd_341ae48c PS1, Line 38: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/b3b34630_616d4c5a PS1, Line 39: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/20e94228_abdf8427 PS1, Line 40: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3598f1ff_48b1c907 PS1, Line 41: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ab09b221_d172fc75 PS1, Line 42: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_BUF(TX_DISABLE) | PAD_IRQ_ROUTE(IOAPIC), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/58b0bcdc_baa7ba56 PS1, Line 43: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/36d57523_c656ca91 PS1, Line 44: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/0b000f0b_84e42db7 PS1, Line 45: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/7316c221_855cbdae PS1, Line 46: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/dec98059_476e5e50 PS1, Line 47: _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/853af8f6_7efce2c0 PS1, Line 48: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/69f72a40_3241fd6d PS1, Line 49: _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3443dafa_ebec9029 PS1, Line 50: _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/5bb99bb2_db12853c PS1, Line 51: _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/2b9bc500_6512be74 PS1, Line 52: _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/495fe802_6d262def PS1, Line 53: _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3ae256ca_2452e50a PS1, Line 54: _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/c0742b75_6289cfbc PS1, Line 55: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/dcec0e4a_37b17eec PS1, Line 58: _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ca2d1c06_7e594ba1 PS1, Line 59: _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/66400631_7abd554e PS1, Line 60: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/1ad3b89a_902befa8 PS1, Line 61: _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e89d21b7_2455d5e4 PS1, Line 62: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/834c4599_d5459d49 PS1, Line 63: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/278edf06_23b265a0 PS1, Line 64: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4bb69de9_d8cb31ad PS1, Line 65: _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/c32fec79_311f745f PS1, Line 66: _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/849ba5e3_8ee7062b PS1, Line 67: _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bda5ca67_538b9029 PS1, Line 68: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e9e84651_90452c54 PS1, Line 71: _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6551bcd8_f60711d6 PS1, Line 72: _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/99510de2_f426497c PS1, Line 75: _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/841f2c1e_6608c857 PS1, Line 76: _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/9c83495c_6bda4d81 PS1, Line 77: _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/97550ad2_a9982767 PS1, Line 78: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6d1f0012_56ea170a PS1, Line 79: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e428e8c3_9bb990c9 PS1, Line 80: _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/5c6f61ec_79748579 PS1, Line 81: _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/100618d6_4b5f22d6 PS1, Line 82: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e76b4fad_21da7024 PS1, Line 83: _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/1ef68a73_e6401e11 PS1, Line 84: _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/cf02272e_ef3fb9bd PS1, Line 87: _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(LEVEL) | PAD_BUF(TX_RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/89d5efe7_7deb2f73 PS1, Line 88: _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/67a4eee8_4eb0f0f3 PS1, Line 89: _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ba95d904_a6060b84 PS1, Line 90: _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/30495774_9fb517c6 PS1, Line 91: _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/6032ad2d_96887e7d PS1, Line 92: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/175667b2_fa00c8c4 PS1, Line 93: _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/7d695028_8389631d PS1, Line 94: _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/2b7046b9_961ce3c6 PS1, Line 95: _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ba77b3a1_1460d0e6 PS1, Line 98: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4ead67c3_e924cde0 PS1, Line 99: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/10838cd3_cea2cc67 PS1, Line 100: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/c88812e4_83d8ac17 PS1, Line 101: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/468d9091_4da03a1c PS1, Line 102: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/c64b5cf8_5e04e432 PS1, Line 103: _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ead78083_2af0246d PS1, Line 104: _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/40154bb0_4d4ac11d PS1, Line 105: _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bcee65ee_b6f048ad PS1, Line 106: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bcde628f_652a403f PS1, Line 107: _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e56f21d8_ad7183fb PS1, Line 108: _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/5249cbb6_d90335b4 PS1, Line 109: _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/847cf6e7_d89f20a0 PS1, Line 110: _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/d9a9b875_b66b0d1a PS1, Line 111: _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/a31e1400_84287834 PS1, Line 112: _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/e3acfdc0_93ca9537 PS1, Line 113: _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/aa7ec7ef_47fa7824 PS1, Line 114: _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/df0a2e7c_96119ae8 PS1, Line 117: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/48d786d7_71b4aebc PS1, Line 118: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4db2abc2_ca9d78fc PS1, Line 119: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/18d00f9b_4439afad PS1, Line 120: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/0ee48896_ef523861 PS1, Line 121: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/2915ce69_9ca4c22b PS1, Line 122: _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/c005063a_6a8bdf78 PS1, Line 123: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/723a9aaa_9eb09ae8 PS1, Line 124: _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/037a798d_744522f7 PS1, Line 125: _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/65dbb28f_acd298f2 PS1, Line 126: _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/b2fd956f_8fa959a2 PS1, Line 127: _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/ab1d082a_4f8c7926 PS1, Line 128: _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/2e603a55_e87bacc3 PS1, Line 131: _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/bed957cc_7770e6a7 PS1, Line 132: _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/859a73a3_d1ef6eff PS1, Line 133: _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/9d2f78e2_61bb17b4 PS1, Line 134: _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/64135070_98de4783 PS1, Line 135: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/3a07c4e5_990b1eb5 PS1, Line 136: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/d5c1f943_9fe60473 PS1, Line 137: _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4bf403b1_3fe4156c PS1, Line 138: _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/4ee5b92c_577af197 PS1, Line 139: _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), line over 96 characters File src/soc/intel/common/block/cse/cse.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/319e379f_e62ae4f8 PS1, Line 826: printk(BIOS_DEBUG, "HECI: Disable ME set %s!\n", status ? "success" : "failure"); line over 96 characters File src/soc/intel/skylake/lockdown.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/545513a2_64caec9d PS1, Line 13: if (chipset_lockdown >= CHIPSET_LOCKDOWN_COREBOOT) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118066): https://review.coreboot.org/c/coreboot/+/52767/comment/44526b2f_dc2d3e3a PS1, Line 18: if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/52767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71d099d6dad529fff79c1ccf30082152a92a284d Gerrit-Change-Number: 52767 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 20:35:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Added LabTop series Added ITE 8987E Added LOCKDIS to mark SPI as writ...
by Star Labs (Code Review) 30 Apr '21

30 Apr '21

Star Labs has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52767 ) Change subject: Added LabTop series Added ITE 8987E Added LOCKDIS to mark SPI as writable in SKL Added CMOS setting to disable ME ...................................................................... Added LabTop series Added ITE 8987E Added LOCKDIS to mark SPI as writable in SKL Added CMOS setting to disable ME Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I71d099d6dad529fff79c1ccf30082152a92a284d --- A Documentation/mainboard/starlabs/labtop.md A src/ec/starlabs/it8987/Kconfig A src/ec/starlabs/it8987/Makefile.inc A src/ec/starlabs/it8987/acpi/ac.asl A src/ec/starlabs/it8987/acpi/battery.asl A src/ec/starlabs/it8987/acpi/cmos.asl A src/ec/starlabs/it8987/acpi/ec.asl A src/ec/starlabs/it8987/acpi/hid.asl A src/ec/starlabs/it8987/acpi/keyboard.asl A src/ec/starlabs/it8987/acpi/lid.asl A src/ec/starlabs/it8987/acpi/thermal.asl A src/ec/starlabs/it8987/chip.h A src/ec/starlabs/it8987/ec.c A src/ec/starlabs/it8987/ec.h A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc A src/mainboard/starlabs/labtop/variants/tgl/board.fmd A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb A src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/tgl/include/variant/gpio.h A src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h A src/mainboard/starlabs/labtop/variants/tgl/romstage.c M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/common/pch/include/intelpch/lockdown.h M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/me.c 76 files changed, 3,908 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/52767/1 diff --git a/Documentation/mainboard/starlabs/labtop.md b/Documentation/mainboard/starlabs/labtop.md new file mode 100644 index 0000000..aa49271 --- /dev/null +++ b/Documentation/mainboard/starlabs/labtop.md @@ -0,0 +1,174 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-10710U (Comet Lake) + - Intel i3-10110U (Comet Lake) + - Intel i7-8550u (Kaby Lake Refresh) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 620 + - GOP driver is recommended, VBT is provided + - eDP 13-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 16GB on-board for Comet Lake platforms[^1] + - 8GB on-board for Kaby Lake Refresh platform. +- Networking + - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) + - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - USB 3.1 Gen 2 Type-C (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: + +Comet Lake and Kaby Lake configurations: +- Intel Flash Descriptor file (descriptor.bin) +- Intel Management Engine firmware (me.bin) + +Comet Lake configuration only: +- ITE IT8987E firmware (it8987-x.xx.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +##### LabTop Mk IV (Comet Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml +make +``` + +##### LabTop Mk III (Kaby Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ +``` +#### **Requirements:** + +* Only available on Star Labtop Mk IV and Star LabTop Mk III +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. Anything higher than **1.5.6** will work. +![fwupd version](https://cdn.shopify.com/s/files/1/2059/5897/files/fwupdV.png?v=161… +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings. +2\. When the BIOS settings load, use the arrow keys to navigate to the advanced tab\. Here you will see BIOS Lock\. +3\. Press `Enter` to change this setting from **Enabled** to **Disabled** + +![Disable BIOS Lock](https://cdn.shopify.com/s/files/1/2059/5897/files/IMG_20210120_094049… + +4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: +![Switch Branch](https://cdn.shopify.com/s/files/1/2059/5897/files/SwitchBranch.png?… +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + +![Installed coreboot](https://cdn.shopify.com/s/files/1/2059/5897/files/Complete.png?v=… +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/src/ec/starlabs/it8987/Kconfig b/src/ec/starlabs/it8987/Kconfig new file mode 100644 index 0000000..ba9e908 --- /dev/null +++ b/src/ec/starlabs/it8987/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_STARLABS_IT8987 + bool + select EC_ACPI + help + Interface to IT8987 embedded controller principally in Star Labs notebooks. diff --git a/src/ec/starlabs/it8987/Makefile.inc b/src/ec/starlabs/it8987/Makefile.inc new file mode 100644 index 0000000..10c9dcd --- /dev/null +++ b/src/ec/starlabs/it8987/Makefile.inc @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +PHONY+=add_ite_fw +INTERMEDIATE+=add_ite_fw + +ifeq ($(CONFIG_EC_STARLABS_IT8987),y) +all-y += ec.c +smm-$(CONFIG_DEBUG_SMI) += ec.c +endif + +ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN),y) + +ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN_PATH),) +files_added:: warn_no_ite_fw +endif + +add_ite_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_IT8987_BIN_PATH) -u +endif + +PHONY+=warn_no_ite_fw +warn_no_ite_fw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the IT8987 EC Firmware.\n" + printf "Do not flash this image. Your LabTop Mk IV's power button\n" + printf "may not respond when you press it.\n\n" + diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl new file mode 100644 index 0000000..860bc86 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/ac.asl @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (ECON == 1) + { + Local0 = 0x0F + } + Else + { + Local0 = 0 + } + Return (Local0) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If (ECWR & 0x01) + { + \PWRS = 1 + } + Else + { + \PWRS = 0 + } + Return (\PWRS) + } +} + +Method (_QA0, 0, NotSerialized) // AC Power Connected +{ + If (ECWR & 0x01) + { + \PWRS = 1 + } + Else + { + \PWRS = 0 + } + + // 500ms delay - Not used in coreboot + // Sleep (500) + Notify (BAT0, 0x81) + // Sleep (500) + Notify (ADP1, 0x80) +} + +Method(_Q0B, 0, NotSerialized) // Battery Connected +{ + // 500ms delay - Not used in coreboot + // Sleep (500) + Notify (BAT0, 0x81) + // Sleep (500) + Notify (BAT0, 0x80) +} diff --git a/src/ec/starlabs/it8987/acpi/battery.asl b/src/ec/starlabs/it8987/acpi/battery.asl new file mode 100644 index 0000000..2dd0d96 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/battery.asl @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + // Battery Slot Status + Method (_STA, 0, Serialized) + { + If (ECWR & 0x02) + { + Return (0x1F) + } + Return (0x0F) + } + + // Default Static Battery Information + Name (BPKG, Package (13) + { + 1, // 0: Power Unit + 0xFFFFFFFF, // 1: Design Capacity + 0xFFFFFFFF, // 2: Last Full Charge Capacity + 1, // 3: Battery Technology(Rechargeable) + 0xFFFFFFFF, // 4: Design Voltage 10.8V + 0, // 5: Design capacity of warning + 0, // 6: Design capacity of low + 0x64, // 7: Battery capacity granularity 1 + 0, // 8: Battery capacity granularity 2 + "CN6613-2S3P", // 9: Model Number + "6UA3", // 10: Serial Number + "Real", // 11: Battery Type + "GDPT" // 12: OEM Information + }) + + Method (_BIF, 0, Serialized) + { + BPKG[1] = B1DC + BPKG[2] = B1FC + BPKG[4] = B1FV + If (B1FC) + { + BPKG[5] = B1FC / 10 + BPKG[6] = B1FC / 25 + BPKG[7] = B1DC / 100 + } + + Return (BPKG) + } + + Name (PKG1, Package (4) + { + 0xFFFFFFFF, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + + Method (_BST, 0, Serialized) + { + + + PKG1[0] = B1ST & 0x07 + If (B1ST & 0x01) + { + PKG1[1] = B1CR + } + Else + { + PKG1[1] = B1CR + } + PKG1[2] = B1RC + PKG1[3] = B1VT + Return (PKG1) + } +} + +// Not used in coreboot +// Device (BAT1) +// { +// Name (_HID, EISAID ("PNP0C0A")) +// Name (_UID, 1) // "Unique" that's the same as BAT0? +// Method (_STA, 0, NotSerialized) +// { +// Return (0x00) +// } +// } + +// Not used in coreboot +// Device (BAT2) +// { +// Name (_HID, EISAID ("PNP0C0A")) +// Name (_UID, 2) +// Method (_STA, 0, NotSerialized) +// { +// Return (0x00) +// } +// } diff --git a/src/ec/starlabs/it8987/acpi/cmos.asl b/src/ec/starlabs/it8987/acpi/cmos.asl new file mode 100644 index 0000000..3368473 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/cmos.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (CMOS, SystemIO, 0x70, 0x02) +Field (CMOS, ByteAcc, NoLock, Preserve) +{ + NVRI, 8, + NVRD, 8 +} + +IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve) +{ + Offset (0x40), + KBBL, 8, // Keyboard backlight timeout + FNSW, 8, // Ctrl Fn Reverse (make keyboard Apple-like) + + Offset (0x7D), + FNLC, 8 // Current state of Fn Lock key. +} diff --git a/src/ec/starlabs/it8987/acpi/ec.asl b/src/ec/starlabs/it8987/acpi/ec.asl new file mode 100644 index 0000000..1efe309 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/ec.asl @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ASL_PVOL_DEFOF_NUM 0xe8 + +Scope(\) +{ + // These fields come from the Global NVS area + Field (GNVS,AnyAcc,Lock,Preserve) + { + Offset(33), + B2SC, 8, // (33) Battery 2 Stored Capacity + Offset(36), + B2SS, 8 // (36) Battery 2 Stored Status + } +} + +Scope (\_SB) +{ + #include "hid.asl" +} + +Scope (\_SB.PCI0) +{ + // Add the entries for the PS/2 keyboard and mouse. + #include <drivers/pc80/pc/ps2_controller.asl> +} + +Scope (\_SB.PCI0.LPCB) +{ + // Include the definitions for accessing CMOS. + #include "cmos.asl" + + // Our embedded controller device. + Device (H_EC) + { + Name (_HID, EISAID ("PNP0C09")) // ACPI Embedded Controller + Name (_UID, 1) + Name (_GPE, EC_GPE_SCI) + + // ECDT (Embedded Controller Boot Resources Table) Check to correct + // ECAV flag in the beginning + Name(ECTK, 1) + Name(ECFG, 0) + Name(WIBT, 0) + Name(APST, 0) + + Name(ECON, 1) // AC debug + Name(BNUM, 0) // Number Of Batteries Present + Name(PVOL, ASL_PVOL_DEFOF_NUM) + Name(B1CC, 0) + Name(B2CC, 0) + + Name(B2ST, 0) + Name(CFAN, 0) + Name(CMDR, 0) + Name(DOCK, 0) + Name(EJET, 0) + Name(MCAP, 0) + Name(PLMX, 0) + Name(PECH, 0) + Name(PECL, 0) + Name(PENV, 0) + Name(PINV, 0) + Name(PPSH, 0) + Name(PPSL, 0) + Name(PSTP, 0) + Name(RPWR, 0) + Name(LIDS, 0) + Name(SLPC, 0) + Name(VPWR, 0) + Name(WTMS, 0) + Name(AWT2, 0) + Name(AWT1, 0) + Name(AWT0, 0) + Name(DLED, 0) + Name(IBT1, 0) + Name(ECAV, 1) // Support DPTF feature + Name(SPT2, 0) + Name(PB10, 0) + Name(IWCW, 0) + Name(IWCR, 0) + Name(BTEN, 0) + Mutex(ECMT, 0) + + Method (_CRS, 0, Serialized) + { + Name (BFFR, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0x00, 0x01) + IO (Decode16, 0x66, 0x66, 0x00, 0x01) + }) + Return (BFFR) + } + + Method (_STA, 0, NotSerialized) + { +// Store (0x03, \_SB.PCI0.GFX0.CLID) + If ((ECON == 1)) + { + Return (0x0F) + } + + Return (0x00) + } + + Name (ECOK, Zero) + Method(_REG, 2, NotSerialized) + { + If ((Arg0 == 0x03) && (Arg1 == 0x01)) + { + ECOS = 1 + ECAV = 1 + + // Unconditionally fix up the Battery and Power State. + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + BNUM = 0 + BNUM |= ((ECRD (RefOf (ECWR)) & 0x02) >> 1) + + // Save the current Power State for later. + // Store (PWRS, Local0) + + // Initialize the Power State. + // BNUM = 0 = Virtual Power State + // BNUM > 0 = Real Power State + If (BNUM == 0x00) + { + \PWRS = ECRD (RefOf (VPWR)) + } + Else + { + \PWRS = (ECRD (RefOf (ECWR)) & 0x01) + } + PNOT() + + /* Initialize LID switch state */ + \LIDS = LIDS + } + + // Flag that the OS supports ACPI. + \_SB.PCI0.LPCB.H_EC.ECOS = 1 + } + + Name (S3OS, Zero) + Method (PTS, 1, Serialized) + { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + S3OS = ECOS + } + \_SB.PCI0.LPCB.H_EC.ECOS = 0 + } + + Method (WAK, 1, Serialized) + { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + ECOS = S3OS + } + \_SB.PCI0.LPCB.H_EC.ECOS = 1 + } + + OperationRegion (SIPR, SystemIO, 0xB2, 0x1) + Field (SIPR, ByteAcc, Lock, Preserve) + { + SMB2, 8 + } + + // EC RAM fields + OperationRegion(ECF2, EmbeddedControl, 0, 0xFF) + Field (ECF2, ByteAcc, Lock, Preserve) + { + XXX0, 8, // EC Firmware main- version number. + XXX1, 8, // EC Firmware sub- version number. + XXX2, 8, // EC Firmware test- version number. + + Offset(0x06), + SKID, 8, // SKU ID + + Offset(0x11), + KBCD, 8, // Key / Touch Pad disable/enable bit + ECOS, 8, // Enter OS flag + HDAO, 8, + ECHK, 8, // Hot keys flag + + Offset(0x18), + KLBS, 8, // Keyboard backlight begin. + KLBE, 8, // Keyboard backlight status. + + Offset(0x1A), + KBLT, 8, // Keyboard Backlight Timeout + PWPF, 8, // Power Profile + + Offset(0x1E), + BTHP,8, // Health Battery Percentage + + Offset(0x20), + RCMD, 8, // Same function as IO 66 port to send EC command + RCST, 8, // Report status for the result of command execution + + Offset(0x2C), + FNST, 8, // FN LOCK key status. + + Offset(0x3F), + SFAN, 8, // Set Fan Speed. + BTMP, 16, // Battery Temperature. + BCNT, 16, // Battery Cycle Count. + FRMP, 16, // Fan Current Speed. + + Offset(0x60), + TSR1, 8, // Thermal Sensor Register 1 [CPU VR (IMVP) Temp on RVP] + TSR2, 8, // Thermal Sensor Register 2 [Heat exchanger fan temp on RVP] + TER4, 8, // Thermal Sensor Register 3 (skin temperature) + + Offset(0x63), + TSI,4, // [0..3] 0 = SEN1 - CPU VR temperature sensor + // 1 = SEN2 - Heat Exchanger temperature sensor + // 2 = SEN3 - Skin temperature sensor + // 3 = SEN4 - Ambient temperature sensor + // 4 = SEN5 - DIMM temperature sensor [IR sensor 1 on WSB] + // 5 = SEN6 - not used on RVP + HYST, 4, // [4..7] - Hysteresis in degC. + TSHT, 8, // Thermal Sensor (N) high trip point(set default value =70) + TSLT, 8, // Thermal Sensor (N) low trip point (set default value =70) + TSSR, 8, // TSSR- thermal sensor status register (set bit2 =1) + // BIT0:SEN1 - CPU VR Temp Sensor Trip Flag + // BIT1:SEN2 - Fan Temp Sensor Trip Flag + // BIT2:SEN3 - Skin Temp Sensor Trip Flag + // BIT3:SEN4 - Ambient Temp Sensor Trip Flag + // BIT4:Reserved + // BIT5:Reserved + // BIT6:Reserved + // BIT7:Reserved + CHGR, 16, // Charge Rate + + Offset(0x70), + CPTM, 8, // CPU Temperature + + Offset(0x72), + TER2, 8, // Charger Temperature, Charger thermistor support + + Offset(0x7F), + LSTE, 1, // Lid feature + // BIT0LID GPI + , 7, // Reserved + + Offset(0x80), + ECWR, 8, // AC & Battery status + XX10, 8, // Battery#1 Model Number Code + XX11, 16, // Battery#1 Serial Number + B1DC, 16, // Battery#1 Design Capacity + B1FV, 16, // Battery#1 Design Voltage + B1FC, 16, // Battery#1 Last Full Charge Capacity + XX15, 16, // Battery#1 Trip Point + B1ST, 8, // Battery#1 State + B1CR, 16, // Battery#1 Present Rate + B1RC, 16, // Battery#1 Remaining Capacity + B1VT, 16, // Battery#1 Present Voltage + BPCN, 8, // Battery#1 Remaining percentage + + // USB Type C Mailbox Interface// PPM->OPM Message In + Offset(0xc0), + MGI0, 8, + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + + // USB Type C Mailbox Interface// OPM->PPM Message Out + MGO0, 8, + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + + // USB Type C UCSI DATA Structure. + VER1, 8, + VER2, 8, + RSV1, 8, + RSV2, 8, + + // PPM->OPM CCI indicator + CCI0, 8, + CCI1, 8, + CCI2, 8, + CCI3, 8, + + // OPM->PPM Control message + CTL0, 8, + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + + Offset(0xF0), + , 3,// BIT0 .. BIT2 Reserved + TPCC, 1,// BIT3 TypeC connection bit + , 2,// BIT4 .. BIT5 Reserved + DRMD, 1,// Bit6 Dual Role Mode. 0->DFP: Host mode; 1->UFP: Device Mode. + , 1,// BIT7 Reserved + } + + Method (ECMD, 0, Serialized) + { + } + + Method (ECWT, 2, Serialized,,, {IntObj, FieldUnitObj}) + { + Local0 = Acquire (ECMT, 1000) + If (Local0 == 0x00) + { + If (ECAV) + { + // Execute write to Embedded Controller + Arg1 = Arg0 + } + Release (ECMT) + } + } + + Method (ECRD, 1, Serialized, 0, IntObj, FieldUnitObj) + { + Local0 = Acquire (ECMT, 1000) + If (Local0 == 0) + { + If (ECAV) + { + // Execute read from Embedded Controller + Local1 = DerefOf (Arg0) + Release (ECMT) + Return (Local1) + } + Else + { + Release (ECMT) + } + } + Return (Local1) + } + + // Include the other parts of the Embedded Controller ASL. + #include "keyboard.asl" + #include "battery.asl" + #include "ac.asl" + #include "lid.asl" + + // Method(_Q45) // SMM Mode - Not used in coreboot + // { + // SMB2 = 0xC1 + // } + } +} diff --git a/src/ec/starlabs/it8987/acpi/hid.asl b/src/ec/starlabs/it8987/acpi/hid.asl new file mode 100644 index 0000000..b0e71da --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/hid.asl @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HMDE, Zero) + Name (HRDY, Zero) + Name (BTLD, Zero) + Name (BTS1, Zero) + Name (HEB1, 0x3003) + + Method (_STA, 0, Serialized) // _STA: Status + { +// If (((OSYS >= 0x07DD) && (HEFE == One))) + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + + Method (HDDM, 0, Serialized) + { + Store ("-----> HDDM", Debug) + Name (DPKG, Package (0x04) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444 + }) + Return (DPKG) + } + + Method (HDEM, 0, Serialized) + { + Store ("-----> HDEM", Debug) + HBSY = Zero + If ((HMDE == Zero)) + { + Return (HIDX) + } + Return (HMDE) + } + + Method (HDMM, 0, Serialized) + { + Store ("-----> HDMM", Debug) + Return (HMDE) + } + + Method (HDSM, 1, Serialized) + { + Store ("-----> HDSM", Debug) + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + Store ("-----> HPEM", Debug) + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While ((Local0 < 0xFA) && HBSY) + { + Sleep (0x04) + Local0++ + } + + If (HBSY == One) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } + + Method (BTNL, 0, Serialized) + { + Store ("-----> BTNL", Debug) + If (CondRefOf (\_SB.PWRB.PBST)) + { + \_SB.PWRB.PBST = Zero + Notify (PWRB, One) // Device Check + } + + BTLD = One +// If ((AEAB == One)) +// { + BTS1 = 0x1F + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } +// Else +// { +// BTS1 = Zero +// } + } + + Method (BTNE, 1, Serialized) + { + Store ("-----> BTNE", Debug) +// If ((AEAB == One)) +// { + BTS1 = ((Arg0 & 0x1E) | One) + \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } + } + + Method (BTNS, 0, Serialized) + { + Store ("-----> BTNS", Debug) +// If ((AEAB == One)) +// { + BTS1 = \_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) +// } + Return (BTS1) + } + + Method (BTNC, 0, Serialized) + { + Store ("-----> BTNC", Debug) +// If ((AEAB == One)) +// { + Return (0x1F) +// } +// Else +// { +// Return (Zero) +// } + } + + Name (HEB2, Zero) + Method (HEBC, 0, Serialized) + { + Store ("-----> HEBC", Debug) +// If ((AHDB == One)) +// { +// Return (\HEB1) +// } +// Else +// { + Return (Zero) +// } + } + + Method (H2BC, 0, Serialized) + { + Store ("-----> H2BC", Debug) +// If ((AHDB == One)) +// { +// Return (\HEB1) +// } +// Else +// { + Return (Zero) +// } + } + + Method (HEEC, 0, Serialized) + { + Store ("-----> HEEC", Debug) +// If ((AHDB == One)) +// { + Return (HEB2) /* \_SB_.HIDD.HEB2 */ +// } +// Else +// { +// Return (Zero) +// } + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("eeec56b3-4442-408f-a792-4edd4d758054"))) + { + If ((One == ToInteger (Arg1))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x03 + }) + } + Case (One) + { + BTNL () + } + Case (0x02) + { + Return (HDMM ()) + } + Case (0x03) + { + HDSM (DerefOf (Arg3 [Zero])) + } + Case (0x04) + { + Return (HDEM ()) + } + Case (0x05) + { + Return (BTNS ()) + } + Case (0x06) + { + BTNE (DerefOf (Arg3 [Zero])) + } + Case (0x07) + { + Return (HEBC ()) + } + Case (0x08) + { + } + Case (0x09) + { + Return (H2BC ()) + } + } + } + } + + Return (Buffer (One) + { + 0x00 + }) + } +} + +Method (PWPR, 0, Serialized) +{ + Notify (HIDD, 0xCE) +} + +Method (PWRR, 0, Serialized) +{ + Notify (HIDD, 0xCF) +} diff --git a/src/ec/starlabs/it8987/acpi/keyboard.asl b/src/ec/starlabs/it8987/acpi/keyboard.asl new file mode 100644 index 0000000..fd7ab97 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/keyboard.asl @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_Q80) // Volume up +{ + Store ("-----> _Q80", Debug) + Notify (\_SB.HIDD, 0xC4) + Notify (\_SB.HIDD, 0xC5) + Store ("<----- _Q80", Debug) +} + +Method(_Q81) // Volume down +{ + Store ("-----> _Q81", Debug) + Notify (\_SB.HIDD, 0xC6) + Notify (\_SB.HIDD, 0xC7) + Store ("<----- _Q81", Debug) +} + +Method(_Q99) // Wireless mode +{ + Store ("-----> _Q99", Debug) + \_SB.HIDD.HPEM(8) + Store ("<----- _Q80", Debug) +} + +Method(_Q06) // Brightness decrease +{ + \_SB.PCI0.GFX0.DECB() +} + +Method(_Q07) // Brightness increase +{ + \_SB.PCI0.GFX0.INCB() +} + +Method(_Q08) // FN lock QEvent +{ + FNLC = FNST +} + +Method(_Q54) // Power Button Event +{ + Store ("-----> _Q54", Debug) + If (CondRefOf (\_SB.PWRB)) + { + Notify(\_SB.PWRB, 0x80) + } + Store ("<----- _Q54", Debug) +} + +Method(_QD5) // 10 second power button press +{ + Store ("-----> _QD5", Debug) + \_SB.PWPR() + Store ("<----- _QD5", Debug) +} + +Method(_QD6) // 10 second power button de-press +{ + Store ("-----> _QD6", Debug) + \_SB.PWRR() + Store ("<----- _QD6", Debug) +} diff --git a/src/ec/starlabs/it8987/acpi/lid.asl b/src/ec/starlabs/it8987/acpi/lid.asl new file mode 100644 index 0000000..22e8eeb --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/lid.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA, 0, NotSerialized) + { + DEBUG = "---> IT8987 LID: _STA" + Return (0x0F) + } + + Method (_PSW, 1, NotSerialized) + { + DEBUG = Concatenate ("---> IT8987 LID: _PSW", ToHexString(Arg0)) + } + + Method (_LID, 0, NotSerialized) + { + DEBUG = "---> IT8987 LID: _LID" + If (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.LSTE)) == 0x01) + { + Local0 = 1 + } + else + { + Local0 = 0 + } + Return (Local0) + } +} + +Method (_Q0C, 0, NotSerialized) // Lid close event +{ + DEBUG = "---> IT8987 LID: Q0C (close event)" + LIDS = 0 + \LIDS = LIDS + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Lid open event +{ + DEBUG = "---> IT8987 LID: Q0D (open event)" + LIDS = 1 + \LIDS = LIDS + Notify (LID0, 0x80) +} diff --git a/src/ec/starlabs/it8987/acpi/thermal.asl b/src/ec/starlabs/it8987/acpi/thermal.asl new file mode 100644 index 0000000..983a6d9 --- /dev/null +++ b/src/ec/starlabs/it8987/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_QF0) // Thermal event. +{ + If (LEqual (DBGS, 0x00)) + { + /* Only handle the numerous thermal events if we are */ + /* NOT doing ACPI Debugging. */ + If (CondRefOf (\_TZ.TZ01)) + { + Notify (\_TZ.TZ01, 0x80) + } + } +} \ No newline at end of file diff --git a/src/ec/starlabs/it8987/chip.h b/src/ec/starlabs/it8987/chip.h new file mode 100644 index 0000000..7c82540 --- /dev/null +++ b/src/ec/starlabs/it8987/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EC_STARLABS_IT8987_CHIP_H +#define _EC_STARLABS_IT8987_CHIP_H + +struct ec_starlabs_it8987_config { + u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ +}; + +#endif /* _EC_ITE_IT8987_CHIP_H */ diff --git a/src/ec/starlabs/it8987/ec.c b/src/ec/starlabs/it8987/ec.c new file mode 100644 index 0000000..0a52cbe --- /dev/null +++ b/src/ec/starlabs/it8987/ec.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> +#include <delay.h> +#include <option.h> + +#include "ec.h" +#include "chip.h" + +void it8987_write_data(u8 addr, u8 data) +{ + outb(addr, IT8987E_ADDR); + outb(data, IT8987E_DATA); +} + +u8 it8987_read_data(u8 addr) +{ + outb(addr, IT8987E_ADDR); + return inb(IT8987E_DATA); +} + +u16 it8987_read_chipid(void) +{ + return((it8987_read_data(0x20) << 8) | it8987_read_data(0x21)); +} + +u16 it8987_get_version(void) +{ + return (ec_read(0x00) << 8) | ec_read(0x01); +} + +static void it8987_init(struct device *dev) +{ + /* u8 val; */ + + if (!dev->enabled) + return; + + if (it8987_read_chipid() != 0x8987) { + printk(BIOS_DEBUG, "IT8987: Device not found.\n"); + return; + } + + printk(BIOS_DEBUG, "IT8987: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + + /* Enable the keyboard backlight support. */ + ec_write(0x18, 0xaa); + ec_write(0x19, 0xdd); + + /* Set the timeout for the keyboard backlight. */ + ec_write(ECRAM_KBL_TIMEOUT, get_int_option("kbl_timeout", 0)); + /* + * Set the correct state for the Ctrl Fn Reverse option. This + * swaps the Ctrl and Fn keys to make it like an Apple keyboard. + */ + ec_write(ECRAM_FN_CTRL_REVERSE, get_int_option("fn_ctrl_swap", 0)); + /* + * Copy the stored state of the fn_lock_state CMOS variable to the + * corresponding location within the EC RAM. + */ + ec_write(ECRAM_FN_LOCK_STATE, get_int_option("fn_lock_state", 0)); +} + +static struct device_operations ops = { + .init = it8987_init, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_starlabs_it8987_ops = { + CHIP_NAME("ITE IT8987 EC") + .enable_dev = enable_dev +}; diff --git a/src/ec/starlabs/it8987/ec.h b/src/ec/starlabs/it8987/ec.h new file mode 100644 index 0000000..32baae7 --- /dev/null +++ b/src/ec/starlabs/it8987/ec.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE IT8987 Embedded Controller. + */ + +#ifndef _EC_STARLABS_IT8987_H +#define _EC_STARLABS_IT8987_H + +/* Command / data ports. */ +#define IT8987E_ADDR 0x4e +#define IT8987E_DATA 0x4f + +/* Logical device number (LDN) assignments. */ +#define IT8987E_SP1 0x01 /* Com1 */ +#define IT8987E_SP2 0x02 /* Com2 */ +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + +/* EC RAM offsets. */ +#define ECRAM_KBL_TIMEOUT 0x07 +#define ECRAM_FN_CTRL_REVERSE 0x08 +#define ECRAM_FN_LOCK_STATE 0x2C + +void it8987_write_data(u8 addr, u8 data); +u8 it8987_read_data(u8 addr); +u16 it8987_read_chipid(void); +u16 it8987_get_version(void); + +#endif diff --git a/src/mainboard/starlabs/Kconfig b/src/mainboard/starlabs/Kconfig new file mode 100644 index 0000000..4df0588 --- /dev/null +++ b/src/mainboard/starlabs/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_STARLABS + +choice + prompt "Mainboard model" + +source "src/mainboard/starlabs/*/Kconfig.name" + +endchoice + +source "src/mainboard/starlabs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Star Labs" + +endif # VENDOR_STARLABS diff --git a/src/mainboard/starlabs/Kconfig.name b/src/mainboard/starlabs/Kconfig.name new file mode 100644 index 0000000..7aab0da --- /dev/null +++ b/src/mainboard/starlabs/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_STARLABS + bool "Star Labs" diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig new file mode 100644 index 0000000..9efcabc --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -0,0 +1,133 @@ +if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_STARBOOK_TGL + +# +# LabTop Mk IV CML Board uses the following devices: +# +# GigaDevice GD25Q64C (8192KB) SPI NOR flash (KBL) +# Winbond 25Q128JVSQ (16384KB) SPI NOR flash (CML) +# Infineon SLB9670VQ SPI TPM2.0 device +# Realtek ALC256 audio CODEC +# ITE IT8987 Embedded Controller +# Analogix ANX7447 crosspoint switch +# +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select BOARD_ROMSIZE_KB_8192 if BOARD_STARLABS_LABTOP_KBL + select DRIVERS_I2C_HID +# select DRIVERS_I2C_GENERIC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select HAVE_IFD_BIN + select HAVE_ME_BIN + select MAINBOARD_HAS_LIBGFXINIT if BOARD_STARLABS_LABTOP_KBL + select EC_STARLABS_IT8987 + select EC_STARLABS_IT8987_BIN if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select SYSTEM_TYPE_LAPTOP + select SPI_FLASH_WINBOND if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select SPI_FLASH_GIGADEVICE if BOARD_STARLABS_LABTOP_KBL + select DISABLE_ACPI_HIBERNATE + select HAVE_OPTION_TABLE + select USE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config MAINBOARD_DIR + string + default "starlabs/labtop" + +config VARIANT_DIR + string + default "tgl" if BOARD_STARLABS_STARBOOK_TGL + default "cml" if BOARD_STARLABS_LABTOP_CML + default "kbl" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_PART_NUMBER + string + default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL + default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML + default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_FAMILY + string + default "B5" if BOARD_STARLABS_STARBOOK_TGL + default "L4" if BOARD_STARLABS_LABTOP_CML + default "L3" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "StarBook" if BOARD_STARLABS_STARBOOK_TGL + default "LabTop" + +config MAX_CPUS + int + default 8 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_STARBOOK_TGL + default 12 + +#config DRIVER_TPM_SPI_CHIP +# int +# default 2 + +config UART_FOR_CONSOLE + int + default 2 + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_0_flashdescriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_2_intel_me.bin" + +config ME_STATE_BY_CMOS + bool + default y + +config EC_STARLABS_IT8987_BIN + bool + default n + default y if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + +config EC_STARLABS_IT8987_BIN_PATH + string + depends on EC_STARLABS_IT8987_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_8_ec.bin" + +#config VGA_BIOS_FILE +# string +# default "pci8086,9b41.rom" if BOARD_STARLABS_LABTOP_CML +# default "pci8086,5917.rom" if BOARD_STARLABS_LABTOP_KBL + +config VGA_BIOS_ID + string + default "8086,9b41" if BOARD_STARLABS_LABTOP_CML + default "8086,5917" if BOARD_STARLABS_LABTOP_KBL + +config TIANOCORE_BOOTSPLASH_FILE + string + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +endif diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name new file mode 100644 index 0000000..8ef8b7b --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -0,0 +1,13 @@ +comment "Star Labs LabTop Mk IV" + +config BOARD_STARLABS_STARBOOK_TGL + bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" + select SOC_INTEL_TIGERLAKE + +config BOARD_STARLABS_LABTOP_CML + bool "Star Labs LabTop Mk IV (i3-10110u and i7-10710u)" + select SOC_INTEL_COMETLAKE_1 + +config BOARD_STARLABS_LABTOP_KBL + bool "Star Labs LabTop Mk IV (i7-8550u)" + select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc new file mode 100644 index 0000000..f89bda7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += ./spd +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += bootblock.c + +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/starlabs/labtop/acpi/ec.asl b/src/mainboard/starlabs/labtop/acpi/ec.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl new file mode 100644 index 0000000..bf73244 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" + + /* Power button device. */ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (PBST, One) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } +} + +/* + * The Intel Comet Lake platform doesn't support SoundWire but there + * is a kernel bug in some 5.10.x releases. + * + * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More + * details can be found at https://bit.ly/3ttdffG but it appears to + * be triggered by missing SoundWire ACPI entries. + * + * Add the minimal set to make it work again. + */ +Scope (_SB.PCI0.HDAS) +{ + Device (SNDW) + { + Name (_ADR, 0x40000000) + + Name (_CID, Package (0x02) + { + "PRP00001", + "PNP0A05" + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0B) + } + } +} + +/* + * ITE IT8987E Embedded Controller + * + * We include this here as we need to support different levels within + * the ACPI DSDT tree structure. + */ +#define EC_GPE_SWI 0x49 /* GPP_E15 */ +#define EC_GPE_SCI 0x50 /* GPP_E16 */ + +#include <ec/starlabs/it8987/acpi/ec.asl> + + diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl new file mode 100644 index 0000000..d8eb818 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.H_EC.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.H_EC.WAK (Arg0) +} diff --git a/src/mainboard/starlabs/labtop/acpi/superio.asl b/src/mainboard/starlabs/labtop/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/board_info.txt b/src/mainboard/starlabs/labtop/board_info.txt new file mode 100644 index 0000000..9543745 --- /dev/null +++ b/src/mainboard/starlabs/labtop/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: LabTop Mk IV +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/labtop/bootblock.c b/src/mainboard/starlabs/labtop/bootblock.c new file mode 100644 index 0000000..5d9cf02 --- /dev/null +++ b/src/mainboard/starlabs/labtop/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <console/console.h> +#include <bootblock_common.h> + +#include "baseboard/variants.h" +#include "variant/gpio.h" + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default new file mode 100644 index 0000000..12b2440 --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +hyper_threading=Enable +kbl_timeout=30 seconds +fn_ctrl_swap=Disable +me_state=Disable diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout new file mode 100644 index 0000000..848168e --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 5 hyper_threading +409 1 e 5 me_state + +# coreboot config options: EC +512 3 e 4 kbl_timeout +520 1 e 1 fn_ctrl_swap + +# coreboot config options: southbridge +536 2 e 6 power_on_after_fail + +#408 1 h 1 preserve_smmstore + +# coreboot config options: check sums +984 16 h 0 check_sum + +# embedded controller settings (outwith the checksummed area) +1000 1 h 0 fn_lock_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 30 seconds +4 1 1 minute +4 2 3 minutes +4 3 5 minutes +4 4 Never + +5 0 Enable +5 1 Disable + +6 0 Disable +6 1 Enable +6 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl new file mode 100644 index 0000000..d0bcf07 --- /dev/null +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> +#if CONFIG(BOARD_STARLABS_LABTOP_CML) || CONFIG(BOARD_STARLABS_STARBOOK_TGL) + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> +#else + #include <soc/intel/skylake/acpi/globalnvs.asl> +#endif + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + + +#elif CONFIG(BOARD_STARLABS_LABTOP_CML) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> +#else + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> +#endif + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/labtop/hda_verb.c b/src/mainboard/starlabs/labtop/hda_verb.c new file mode 100644 index 0000000..34bb4af --- /dev/null +++ b/src/mainboard/starlabs/labtop/hda_verb.c @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "variant/hda_verb.h" + diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c new file mode 100644 index 0000000..b0073c7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> +#include <types.h> +#include <uuid.h> + +#include <ec/starlabs/it8987/ec.h> + +/* Override the BIOS version using smbios_mainboard_bios_version() */ +const char *smbios_mainboard_bios_version(void) +{ +#if CONFIG_BOARD_STARLABS_STARBOOK_TGL + return "CB_0"; +#else + return "CB_5"; +#endif +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it8987_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +/* Override smbios_system_manufacturer */ +const char *smbios_system_manufacturer(void) +{ + return "Star Labs"; +} + +/* Override smbios_system_sku */ +const char *smbios_system_sku(void) +{ +#if CONFIG_BOARD_STARLABS_STARBOOK_TGL + return "B5"; +#elif CONFIG_BOARD_STARLABS_LABTOP_CML + return "L4"; +#else + return "L3-U"; +#endif +} + +/* Override smbios_mainboard_features_flags */ +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAG_HOSTING_BOARD | SMBIOS_FEATURE_FLAG_REPLACEABLE; +} + +/* Override smbios_mainboard_location_in_chassis */ +const char *smbios_mainboard_location_in_chassis(void) +{ + return "Default"; +} + +/* Override smbios_mainboard_board_type */ +smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_MOTHERBOARD; +} + +/* Override smbios_mainboard_asset_tag */ +const char *smbios_mainboard_asset_tag(void) +{ + return "Default"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +/* Override smbios_chassis_version */ +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +/* Override smbios_chassis_serial_number */ +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +/* Override smbios_chassis_asset_tag */ +const char *smbios_chassis_asset_tag(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} diff --git a/src/mainboard/starlabs/labtop/ramstage.c b/src/mainboard/starlabs/labtop/ramstage.c new file mode 100644 index 0000000..5ba0778 --- /dev/null +++ b/src/mainboard/starlabs/labtop/ramstage.c @@ -0,0 +1,25 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/ramstage.h> +#include <option.h> +#include "variant/gpio.h" + +#if CONFIG(BOARD_STARLABS_LABTOP_CML) +void mainboard_silicon_init_params(FSPS_UPD * supd) +#else +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +#endif +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc new file mode 100644 index 0000000..ca39059 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Schematics for this platform show Samsung K4A8G165WB-BCRC devices +# which are 8Gb, 2400Mbps 512Mx16 devices. +# +# The hardware platforms used for testing are fitted with a Micron part +# which has the FBGA identifier "D9ZFW". The identification tool at +# https://www.micron.com/support/tools-and-utilities/fbga identifies +# this as the MT40A1G16KD-062E:E. These are 16Gb, 1Gx16 devices. +# +# We have defined both SPD options below. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron-MT40A1G16KD-062E-E # 0b0001 +SPD_SOURCES += empty_ddr4 # 0b0010 +SPD_SOURCES += empty_ddr4 # 0b0011 +SPD_SOURCES += empty_ddr4 # 0b0100 +SPD_SOURCES += empty_ddr4 # 0b0101 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0110 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) \ No newline at end of file diff --git a/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex b/src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex new file mode 100644 index 0000000..273cd02 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/gskill-F4-3200C22S.hex @@ -0,0 +1,33 @@ +# G.Skill F4-3200C22S +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47 +34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000..1777847 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex b/src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex new file mode 100644 index 0000000..4fe4d0e --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 33 47 32 45 31 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex new file mode 100644 index 0000000..36b85a2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex @@ -0,0 +1,33 @@ +# K4A8G165WB-BCRC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 0B E3 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 42 42 30 2D 43 52 43 20 20 20 20 00 80 CE +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/spd.h b/src/mainboard/starlabs/labtop/spd/spd.h new file mode 100644 index 0000000..6cd9416 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include <variant/gpio.h> + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/starlabs/labtop/spd/spd_util.c b/src/mainboard/starlabs/labtop/spd/spd_util.c new file mode 100644 index 0000000..7d23dfb --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd_util.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = {{0, 6, 3, 1, 5, 2, 7, 4}, {7, 5, 3, 6, 2, 4, 0, 1} }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h new file mode 100644 index 0000000..47e2688 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MEMORY_H +#define MEMORY_H + +u8 get_memory_config_straps(void); +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h new file mode 100644 index 0000000..cfcc6ab --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..454749f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include <soc/gpio.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc new file mode 100644 index 0000000..79b824b --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd new file mode 100644 index 0000000..9018104 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 16M { + BIOS@0x400000 0xC00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt new file mode 100644 index 0000000..bae9210 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb new file mode 100644 index 0000000..b208190 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -0,0 +1,209 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue +# register "SendVrMbxCmd" = "2" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# Graphics (soc/intel/cannonlake/graphics.c) + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "ScsEmmcHs400Enabled" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Enable eDP device + register "DdiPortEdp" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + + # Disable S0ix + register "s0ix_enable" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal Device + register "Device4Enable" = "1" + end + device pci 08.0 on end # Gaussian Mixture Model + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # SD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CNVi Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "0" + + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "0" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC - not fitted + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (SSD x4) + device pci 00.0 on end + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 (LAN) + device pci 1d.5 off end # PCI Express Port 14 (WLAN) + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00fc0201" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x000c0081" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x119e + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h new file mode 100644 index 0000000..4c99674 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_GPIO_H_ +#define _VARIANT_GPIO_H_ + +#include "baseboard/variants.h" + +#ifndef __ACPI__ + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + /* GPIO Community 0 - GPP_E */ + _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + + /* GPIO Community 1 - GPP_H */ + _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + // GPIO Community 0 - GPP_A + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_BUF(TX_DISABLE) | PAD_IRQ_ROUTE(IOAPIC), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + + // GPIO Community 0 - GPP_B + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + + // GPIO Community 0 - GPP_G + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + + // GPIO Community 1 - GPP_D + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + + // GPIO Community 1 - GPP_F + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(LEVEL) | PAD_BUF(TX_RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), + + // GPIO Community 1 - GPP_H + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + + // GPIO Community 4 - GPP_C + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + + // GPIO Community 4 - GPP_E + _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, PAD_PULL(NONE)), + _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | PAD_RX_POL(INVERT), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NONE)), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +#endif + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h new file mode 100644 index 0000000..190474f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _HDA_VERB_H_ +#define _HDA_VERB_H_ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID: 0x10EC119E */ + 0x0017209E, + 0x00172111, + 0x001722EC, + 0x00172310, + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x02ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x022b1010), + /* ONE DOES NOT SIMPLY + MAKE IT WORK WITH WINDOWS */ + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c new file mode 100644 index 0000000..a74d5b1 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <gpio.h> +#include <string.h> +#include <types.h> + +#include "baseboard/memory.h" + +u8 get_memory_config_straps(void) +{ + int memid = 0; + + /* + * The hardware supports a number of different memory configurations + * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6), + * ID1 (GPP_E23) and ID0 (GPP_E22). + * + * The mapping is defined in the schematics as follows ID3 is always + * 0 and can be ignored): + * + * ID2 ID1 ID0 Memory type + * --- --- --- ----------- + * 1 1 1 Samsung 4G single channel + * 1 1 0 Samsung 8G dual channel + * 1 0 1 Micron 4G single channel + * 1 0 0 Micron 8G dual channel + * 0 1 1 Hynix 4G single channel + * 0 1 0 Hynix 8G dual channel + * 0 0 1 Micron 16G dual channel + * 0 0 0 Hynix 16G dual channel + * + * We return the value of these bits so that the index into the SPD + * table can be .spd[] values can be configured correctly in the + * memory configuration structure. + */ + + memid = (gpio_get(GPP_H6) < 2) | (gpio_get(GPP_E23) < 1) | gpio_get(GPP_E22); + + return (u8)memid; +} + +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + u8 memid; + + struct cnl_mb_cfg std_memcfg = { + /* + * The dqs_map arrays map the DDR4 pins to the SoC pins + * for both channels. + * + * the index = pin number on DDR4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 6, 1, 3, 5, 2, 7, 4}, + .dqs_map[DDR_CH1] = {7, 5, 3, 6, 2, 4, 0, 1}, + + /* + * Mainboard uses 121, 81 and 100 rcomp resistors. See R6E1, R6E2 + * and R6E3 on page 6 of the schematics. + */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Mainboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* + * Mainboard is a non-interleaved design - see pages 5 & 6 + * of the schematics. + */ + .dq_pins_interleaved = 0, + + /* + * Mainboard is using DDR_VREF_CA for CH_A and DDR1_VREF_DQ for + * CH_B - see page 5 of the schematics. + */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, + }; + + memcpy(mem_cfg, &std_memcfg, sizeof(std_memcfg)); + + memid = get_memory_config_straps(); + printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid); + + /* + * If we are using single channel ID = 3, 5 or 7 then we only + * populate .spd[0]. If we are dual channel then we also populate + * .spd[2] as well. + */ + mem_cfg->spd[0].read_type = READ_SPD_CBFS; + mem_cfg->spd[0].spd_spec.spd_index = memid; + if (memid != 3 && memid != 5 && memid != 7) { + mem_cfg->spd[2].read_type = READ_SPD_CBFS; + mem_cfg->spd[2].spd_spec.spd_index = memid; + } + + return mem_cfg; +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg board_memcfg; + + cannonlake_memcfg_init(&memupd->FspmConfig, get_memory_cfg(&board_memcfg)); +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc new file mode 100644 index 0000000..e04a8db --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd new file mode 100644 index 0000000..08bc519 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd @@ -0,0 +1,13 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 8M { + BIOS@0x200000 0x600000 { + RW_MRC_CACHE@0x0 0x10000 + SMMSTORE@0x10000 0x40000 + CONSOLE@0x50000 0x20000 + FMAP@0x70000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt new file mode 100644 index 0000000..b7146c5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb new file mode 100644 index 0000000..c7c1ae2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb @@ -0,0 +1,202 @@ +chip soc/intel/skylake + # Disable DEEP + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + + # Enable "Intel Speed Shift Technology" + # register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT_LOCKDIS, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + # register "SendVrMbxCmd" = "2" + +# Graphics (soc/intel/skylake/graphics.c) + register "panel_cfg" = "{ + .up_delay_ms= 200,// T3 + .down_delay_ms= 0,// T10 + .cycle_delay_ms = 500,// T12 + .backlight_on_delay_ms=50,// T7 + .backlight_off_delay_ms = 0,// T9 + .backlight_pwm_hz = 200, + }" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# CPU (soc/intel/skylake/chip.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0]= PchSerialIoPci, + [PchSerialIoIndexI2C1]= PchSerialIoPci, + [PchSerialIoIndexI2C2]= PchSerialIoPci, + [PchSerialIoIndexI2C3]= PchSerialIoPci, + [PchSerialIoIndexI2C4]= PchSerialIoDisabled, + [PchSerialIoIndexI2C5]= PchSerialIoPci, + [PchSerialIoIndexSpi0]= PchSerialIoPci, + [PchSerialIoIndexSpi1]= PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # Power + register "PmConfigSlpS3MinAssert" = "3" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "2" # 500ms + register "PmConfigSlpAMinAssert" = "4" # 2s + +# PM Util (soc/intel/skylake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_C" + register "gpe0_dw2" = "GPP_E" + + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal Device + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # uSD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Actual Bluetooth port + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "0" + register "SataMode" = "0" + + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "0" + + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "0" + end + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #4 + device pci 19.2 off end # I2C #5 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + register "PcieRpLtrEnable[5]" = "1" + chip drivers/wifi/generic + device pci 00.0 on end + end + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9(SSD x4) + device pci 00.0 on end + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" + register "PcieRpClkSrcNumber[8]" = "0" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00000069" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x0000006d" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + subsystemid 0x10ec 0x111e + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h new file mode 100644 index 0000000..05af1d3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/gpio.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_GPIO_H_ +#define _VARIANT_GPIO_H_ + +#include "baseboard/variants.h" + +#ifndef __ACPI__ + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000300, 0x0000), +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A7, 0x44000300, 0x0000), +_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +_PAD_CFG_STRUCT(GPP_A10, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x1000), +_PAD_CFG_STRUCT(GPP_A12, 0x44000300, 0x0000), +_PAD_CFG_STRUCT(GPP_A13, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A15, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x3000), +_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_B6, 0x44000102, 0x1000), +_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x1000), +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x1000), +_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x1000), +_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_B14, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x3000), +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x3000), +_PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C3, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C4, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C5, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x3000), +_PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000), +_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x3000), +_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x3000), +_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x3000), +_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x3000), +_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x3000), +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_C22, 0x44000300, 0x0000), +_PAD_CFG_STRUCT(GPP_C23, 0x80100102, 0x3000), +_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D20, 0x44000201, 0x3000), +_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000), +_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E6, 0x04000700, 0x0000), +_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_E14, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0000), +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0000), +_PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0000), +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0000), +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), +_PAD_CFG_STRUCT(GPP_E20, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E21, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_E23, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x1000), +_PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x1000), +_PAD_CFG_STRUCT(GPP_F10, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x1000), +_PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x1000), +_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x1000), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +#endif + +#endif + + diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h new file mode 100644 index 0000000..f60a51f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/hda_verb.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _HDA_VERB_H_ +#define _HDA_VERB_H_ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC111E */ + 0x0017201E, + 0x00172111, + 0x001722EC, + 0x00172310, + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x15, 0x042B1010), + AZALIA_PIN_CFG(0, 0x17, 0x411111F0), + AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + /* Widget node 0x20 */ + 0x02050018, + 0x02040184, /* Stock: 0x02043984 */ + 0x0205001C, + 0x02040800, + /* Widget node 0x20 - 1 */ + 0x02050024, + 0x02040000, + 0x02050004, + 0x02040080, + /* Widget node 0x20 - 2 */ + 0x02050008, + 0x02040300, + 0x0205000C, + 0x02043F00, + /* Widget node 0x20 - 3 */ + 0x02050015, + 0x02048002, + 0x02050015, + 0x02048002, + /* Widget node 0x0C */ + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + +#endif + diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c new file mode 100644 index 0000000..790f87c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd_util.c" +#include "spd/spd.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + /* Use the correct entry in the SPD table defined in Makefile.inc */ + u8 spd_index = 6; + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + /* struct region_device spd_rdev; */ + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + /* Memory leak is ok since we have memory mapped boot media */ + // TODO evaluate google/eve way of loading + mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); + if (!mem_cfg->MemorySpdPtr00) + die("spd.bin not found\n"); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc new file mode 100644 index 0000000..79b824b --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/labtop/variants/tgl/board.fmd b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd new file mode 100644 index 0000000..9018104 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 16M { + BIOS@0x400000 0xC00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb new file mode 100644 index 0000000..d93d38e --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -0,0 +1,287 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Disable DPTF + register "dptf_enable" = "0" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + +# Finalize (soc/intel/tigerlake/finalize.c) + # PM Timer Disabled, saves power + register "PmTimerDisabled" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # System Agent dynamic frequency support + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Read LPM_EN, make sure to invert the bits + # sudo devmem2 0xfe001c78 + # 0x9 + register "LpmStateDisableMask" = " + LPM_S0i2_1 | + LPM_S0i2_2 | + LPM_S0i3_1 | + LPM_S0i3_2 | + LPM_S0i3_3 | + LPM_S0i3_4 + " + + # Thermal + # rdmsr --bitfield 31:24 --decimal 0x1A2 + register "tcc_offset" = "12" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + # TODO: 0x703 + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + end + device ref dptf on + register "Device4Enable" = "1" + end + device ref peg on + # PCIe PEG0 x4, Clock 3 (SSD1) + register "PcieClkSrcUsage[3]" = "0x40" + register "PcieClkSrcClkReq[3]" = "3" + + register "HybridStorageMode" = "0" + end + device ref tbt_pcie_rp0 on end # J_TYPEC1 + device ref gna on end + device ref north_xhci on # J_TYPEC1 + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # J_TYPEC1 + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + device generic 0 on end + end + end + + # From PCH EDS(576591) + device ref cnvi_bt on end + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + end + end + end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref i2c1 on + #TODO: USB-PD? + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on + register "HeciEnabled" = "1" + end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref sata on + # SATA1 (SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + register "SataSalpSupport" = "1" + end + device ref pcie_rp3 on + # PCIe root port #3 x1, Clock 1 (WLAN) + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieClkSrcUsage[1]" = "2" + register "PcieClkSrcClkReq[1]" = "1" + end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 2 (CARD) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + end + device ref pcie_rp9 off end + device ref pch_espi on + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0E01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0F01" + # LPC TPM + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC1 + register "usb2_port_number" = "3" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x10ec 0x119e + register "PchHdaAudioLinkHdaEnable" = "1" + end + device ref smbus on + register "SmbusEnable" = "1" + end + device ref fast_spi on end + end +end diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/gpio.h new file mode 100644 index 0000000..d7dd9ec --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/gpio.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_GPIO_H_ +#define _VARIANT_GPIO_H_ + +#include "baseboard/variants.h" + +#ifndef __ACPI__ + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +#endif + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h new file mode 100644 index 0000000..0e86541 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/hda_verb.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _HDA_VERB_H_ +#define _HDA_VERB_H_ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC119E */ + 0x0017209E, + 0x00172111, + 0x001722EC, + 0x00172310, + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x40700001), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + +#endif + diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c new file mode 100644 index 0000000..7441292 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/util.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_ddr4_cfg board_cfg = { + .dq_pins_interleaved = 0, + .ect = 0, +}; + +static const struct spd_info spd = { + .topology = MIXED, + .md_spd_loc = SPD_CBFS, + .cbfs_index = 0, + .smbus_info[1] = { + .addr_dimm0 = 0x52, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.SaOcSupport = 1; + const bool half_populated = false; + meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated); +} diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 7bbe1ae..e949716 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -154,5 +154,8 @@ hfsts6.fields.txt_support ? "YES" : "NO"); } +#if CONFIG(ME_STATE_BY_CMOS) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, disable_me, NULL); +#endif BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c6f87b4..2beb5a5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -14,6 +14,8 @@ #include <soc/me.h> #include <string.h> #include <timer.h> +#include <option.h> +#include <types.h> #define MAX_HECI_MESSAGE_RETRY_COUNT 5 @@ -794,6 +796,37 @@ return resp.status; } +void disable_me(void *unused) +{ + /* First check if ME should be disabled */ + u8 me_state = get_int_option("me_state", 0xff); + printk(BIOS_DEBUG, "CMOS: me_state = %d\n", me_state); + if (me_state == 1) { + printk(BIOS_DEBUG, "HECI: Sending command to disable\n"); + int status; + + struct mkhi_hdr reply; + struct disable_command { + struct mkhi_hdr hdr; + uint32_t rule_id; + uint8_t rule_len; + uint32_t rule_data; + } __packed; + struct disable_command msg = { + .hdr = { + .group_id = 0x03, + .command = 0x03, + }, + .rule_id = 6, + .rule_len = 4, + .rule_data = 0, + }; + size_t reply_size; + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + printk(BIOS_DEBUG, "HECI: Disable ME set %s!\n", status ? "success" : "failure"); + } +} + void print_me_fw_version(void *unused) { struct version { diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index be2af4a..8e2227f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -10,6 +10,7 @@ enum { CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ + CHIPSET_LOCKDOWN_COREBOOT_LOCKDIS, /* coreboot leaves lock disabled */ }; /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 1a95e2e..e20817a 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -169,6 +169,9 @@ */ int cse_hmrfpo_get_status(void); +/* Method for disabling the ME */ +void disable_me(void *unused); + /* Fixed Address MEI Header's Host Address field value */ #define BIOS_HOST_ADDR 0x00 diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index 22d7147..32f9ef2 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -9,6 +9,7 @@ * Return values: * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown IPs * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs + * 2 = CHIPSET_LOCKDOWN_COREBOOT_LOCKDIS = Use coreboot but leave lock disabled */ int get_lockdown_config(void); diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index d9495a4..865233a 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -16,6 +16,7 @@ * Return values: * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown IPs * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs + * 2 = CHIPSET_LOCKDOWN_COREBOOT_LOCKDIS = Use coreboot but leave lock disable */ int get_lockdown_config(void) { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d4e8341..aba14e0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -420,7 +420,7 @@ * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + if (get_lockdown_config() >= CHIPSET_LOCKDOWN_COREBOOT) { tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 2fa53c9..4379652 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -9,9 +9,13 @@ static void lpc_lockdown_config(int chipset_lockdown) { - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* Set BIOS Interface Lock */ + if (chipset_lockdown >= CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); + } + + /* Set BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_lock_enable(); } } diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 89491f8..d85c83d 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -361,4 +361,7 @@ * This can't be put in intel_me_status because by the time control * reaches there, ME doesn't respond to GET_FW_VERSION command. */ +#if CONFIG(ME_STATE_BY_CMOS) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, disable_me, NULL); +#endif BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 177010c..bfee1c0 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -1,8 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/device.h> +#include <intelblocks/cse.h> #include <intelblocks/smihandler.h> +#include <soc/soc_chip.h> +#include <soc/pci_devs.h> #include <soc/pm.h> +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from CNP chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + if (!CONFIG(HECI_DISABLE_USING_SMM)) + return; + + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + if (!is_dev_enabled(dev)) + heci_disable(); +} + const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a299..27d87e0 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -162,6 +162,8 @@ printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } - +#if CONFIG(ME_STATE_BY_CMOS) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, disable_me, NULL); +#endif BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/52767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71d099d6dad529fff79c1ccf30082152a92a284d Gerrit-Change-Number: 52767 Gerrit-PatchSet: 1 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
by Felix Held (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52763 ) Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52763/comment/4d58c5fa_afc4a724 PS1, Line 9: GPIOs can only be updated in gpio_configure_pads_with_override() if they : are present in the base table. If they are not there, the override : does not work. This allows them to be in the base table so that they can : be overridden without changing the existing configuration. > have a look at CB:43050 that might be the proper fix instead of this workaround. […] talked with Martin and the scopes of those two things are a bit different, so it's probably a good idea to have both. i'm still not sure if i really like the gpio-nop macro; it is at least a little odd, but i don't dislike it enough to not be ok with adding it. that gpios that are present in the gpio override table, but not in the gpio base table get ignored is still a bug though; planning to rebase and look into CB:43050 to get that one fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/52763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e5e7b7d30f2c89fa1db375ddba394e6914d97b9 Gerrit-Change-Number: 52763 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 20:21:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit April 2021