coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49535 ) Change subject: nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h> Also rename 'reg' to 'reg32'. Change-Id: Id741f636162a8a228bca069637993422deb5e09c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/bootblock.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 9c45f7e..e2cabdb 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> #include "gm45.h" @@ -31,7 +31,7 @@ * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id741f636162a8a228bca069637993422deb5e09c Gerrit-Change-Number: 49535 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49536 ) Change subject: nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h> Also rename 'reg' to 'reg32'. Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/bootblock.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 64e2258..0bb8ae2 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "haswell.h" static uint32_t encode_pciexbar_length(void) @@ -28,7 +29,7 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe Gerrit-Change-Number: 49536 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49540 ) Change subject: nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h> Also rename 'reg' to 'reg32'. Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/bootblock.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 529f4f8..92f9aee 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "sandybridge.h" static uint32_t encode_pciexbar_length(void) @@ -28,7 +29,7 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e Gerrit-Change-Number: 49540 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50164 ) Change subject: mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h> ...................................................................... mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h> Change-Id: If5c35f3518e2cc4d5760a64e0d38fc4843af498a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50164 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/stout/smihandler.c 4 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/butterfly/smihandler.c b/src/mainboard/google/butterfly/smihandler.c index 6b9ec5a..71e7aad 100644 --- a/src/mainboard/google/butterfly/smihandler.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/nvs.h> diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 8d4b4bd..fa9f9f9 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/nvs.h> diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index c434860..c16a0f5 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/google/stout/smihandler.c b/src/mainboard/google/stout/smihandler.c index d282bc7..7412294 100644 --- a/src/mainboard/google/stout/smihandler.c +++ b/src/mainboard/google/stout/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_gnvs.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/smm.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5c35f3518e2cc4d5760a64e0d38fc4843af498a Gerrit-Change-Number: 50164 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49745 ) Change subject: nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR ...................................................................... nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR They aren't necessary. Removing them changes the binary because the corresponding access macros no longer perform pointer arithmetics. Change-Id: I9723a00b58ee35befdce6a3a51aa2b1fce8efa80 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49745 Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/i945/memmap.h 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/northbridge/intel/i945/memmap.h b/src/northbridge/intel/i945/memmap.h index a890445..fcda447 100644 --- a/src/northbridge/intel/i945/memmap.h +++ b/src/northbridge/intel/i945/memmap.h @@ -5,13 +5,8 @@ /* Northbridge BARs */ #define DEFAULT_X60BAR 0xfed13000 -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/49745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9723a00b58ee35befdce6a3a51aa2b1fce8efa80 Gerrit-Change-Number: 49745 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50130 ) Change subject: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ ...................................................................... soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h 3 files changed, 10 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f2a8f377..0dd1456 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -84,9 +84,6 @@ register "PchPcieRpEnable[2]" = "1" register "PchPcieRpEnable[3]" = "1" - # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" - register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 7289e02..806c91b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -139,10 +139,15 @@ int default MAX_PCH_ROOT_PORTS -config MAX_PCIE_CLOCKS +config MAX_PCIE_CLOCK_SRC int - default 10 if SOC_INTEL_ALDERLAKE_PCH_M - default 12 + default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 7 + +config MAX_PCIE_CLOCK_REQ + int + default 6 if SOC_INTEL_ALDERLAKE_PCH_M + default 10 config SMM_TSEG_SIZE hex diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 70ceba7..0f932ce 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -131,10 +131,10 @@ /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ]; /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; -- To view, visit https://review.coreboot.org/c/coreboot/+/50130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Gerrit-Change-Number: 50130 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/vboot: Add config for GBB_FLAG_ENABLE_UDC
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50110 ) Change subject: security/vboot: Add config for GBB_FLAG_ENABLE_UDC ...................................................................... security/vboot: Add config for GBB_FLAG_ENABLE_UDC This change adds the missing `GBB_FLAG_ENABLE_UDC` as a config in vboot/Kconfig (just like the other GBB flags) and uses its value to configure GBB_FLAGS Makefile variable. This is done to allow the mainboard to configure GBB flags by selecting appropriate configs in Kconfig. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I6b397713d643cf9461294e6928596dc847ace6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50110 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e774478..e202333 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -338,6 +338,10 @@ bool "Disable Firmware Management Parameters (FWMP)" default n +config GBB_FLAG_ENABLE_UDC + bool "Enable USB Device Controller" + default n + endmenu # GBB menu "Vboot Keys" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 4cf8090..1703748 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -226,6 +226,7 @@ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_LID_SHUTDOWN),0x1000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ + $(call bool-to-mask,$(CONFIG_GBB_FLAG_ENABLE_UDC),0x10000) \ ) ifneq ($(CONFIG_GBB_BMPFV_FILE),) -- To view, visit https://review.coreboot.org/c/coreboot/+/50110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b397713d643cf9461294e6928596dc847ace6bd Gerrit-Change-Number: 50110 Gerrit-PatchSet: 6 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
by Arthur Heymans (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: HAOUAS Elyes. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49537 ) Change subject: nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Gerrit-Change-Number: 49537 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 01 Feb 2021 08:55:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: bayhub bh720: Add helpers to access PCR registers
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49925 ) Change subject: bayhub bh720: Add helpers to access PCR registers ...................................................................... bayhub bh720: Add helpers to access PCR registers The BH720 PCR registers are accessed using an index/data register pair. Introduce some helper functions to clarify the PCR register operations. Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/drivers/generic/bayhub/bh720.c 1 file changed, 26 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 40788cd..58a5017 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -12,49 +12,45 @@ #include "chip.h" #include "bh720.h" +static u32 bh720_read_pcr(u32 sdbar, u32 addr) +{ + write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | addr); + return read32((void *)(sdbar + BH720_MEM_RW_DATA)); +} + +static void bh720_write_pcr(u32 sdbar, u32 addr, u32 data) +{ + write32((void *)(sdbar + BH720_MEM_RW_DATA), data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | addr); +} + +static void bh720_rmw_pcr(u32 sdbar, u32 addr, u32 clear, u32 set) +{ + u32 data = bh720_read_pcr(sdbar, addr); + data &= ~clear; + data |= set; + bh720_write_pcr(sdbar, addr, data); +} + static void bh720_program_hs200_mode(struct device *dev) { - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + u32 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* Enable Memory Access Function */ write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + bh720_write_pcr(sdbar, 0xd0, 0x80000000); /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + bh720_rmw_pcr(sdbar, BH720_PCR_EMMC_SETTING, 0, BH720_PCR_EMMC_SETTING_1_8V); /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + bh720_rmw_pcr(sdbar, BH720_PCR_DrvStrength_PLL, 0xffff << 16, 0x2510 << 16); /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); + bh720_rmw_pcr(sdbar, BH720_PCR_CSR, 0, BH720_PCR_CSR_EMMC_MODE_SEL); /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + bh720_write_pcr(sdbar, 0xd0, 0x80000001); write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4 Gerrit-Change-Number: 49925 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/i82801gx,ix: Drop MPEN from GNVS
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50120 ) Change subject: sb/intel/i82801gx,ix: Drop MPEN from GNVS ...................................................................... sb/intel/i82801gx,ix: Drop MPEN from GNVS It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/cpu/intel/speedstep/acpi/cpu.asl M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/i82801ix/lpc.c 8 files changed, 9 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 2beb890..f1c5b99 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -133,4 +133,8 @@ acpigen_write_processor_package("PPKG", 0, cores_per_package); acpigen_write_processor_cnot(cores_per_package); + + acpigen_write_scope("\\"); + acpigen_write_name_integer("MPEN", numcpus > 1); + acpigen_pop_len(); } diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl index 417ee11..770acdf 100644 --- a/src/cpu/intel/speedstep/acpi/cpu.asl +++ b/src/cpu/intel/speedstep/acpi/cpu.asl @@ -5,6 +5,7 @@ External (\_SB_.CP00, DeviceObj) External (\_SB_.CP00._PPC) External (\_SB_.CP01._PPC) +External (\MPEN, IntObj) Method (PNOT) { diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index dfd5a56..1e3889b 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -45,7 +45,7 @@ /* Processor Identification */ Offset (0x28), , 8, // 0x28 - Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index d9e01df..b2a6baa 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -41,7 +41,7 @@ u8 rsvd3[3]; /* Processor Identification */ u8 unused_was_apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6c48e9c..a8bc7e3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -12,7 +12,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -21,7 +20,6 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> -#include <soc/nvs.h> #include "chip.h" #include "i82801gx.h" @@ -464,12 +462,6 @@ outb(POST_OS_BOOT, 0x80); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* MPEN, Enable Multi Processing. */ - gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 24efba6..d2af885 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -46,7 +46,7 @@ /* Processor Identification */ Offset (0x28), , 8, // 0x28 - Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 4fa5676..2d4980b 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -41,7 +41,7 @@ u8 rsvd3[3]; /* Processor Identification */ u8 unused_was_apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 5400237..b84b458 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,7 +12,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <string.h> @@ -21,7 +20,6 @@ #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> -#include <soc/nvs.h> #define NMI_OFF 0 @@ -452,12 +450,6 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* MPEN, Enable Multi Processing. */ - gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; -- To view, visit https://review.coreboot.org/c/coreboot/+/50120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8 Gerrit-Change-Number: 50120 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021