coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP]mb/amd/majolica: Set the eSPI to eSPI channel 1.
by Bao Zheng (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50188 to review the following change. Change subject: [WIP]mb/amd/majolica: Set the eSPI to eSPI channel 1. ...................................................................... [WIP]mb/amd/majolica: Set the eSPI to eSPI channel 1. Change-Id: Ifd398e64b1bcb46834e1b0f446cdf407825f7db8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/bootblock.c M src/mainboard/amd/majolica/early_gpio.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50188/1 diff --git a/src/mainboard/amd/majolica/bootblock.c b/src/mainboard/amd/majolica/bootblock.c index f768f3f..6d81857 100644 --- a/src/mainboard/amd/majolica/bootblock.c +++ b/src/mainboard/amd/majolica/bootblock.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/southbridge.h> #include "gpio.h" void bootblock_mainboard_early_init(void) { mainboard_program_early_gpios(); + fch_espi_channel_sel(1); } diff --git a/src/mainboard/amd/majolica/early_gpio.c b/src/mainboard/amd/majolica/early_gpio.c index 916d679..efd06f0 100644 --- a/src/mainboard/amd/majolica/early_gpio.c +++ b/src/mainboard/amd/majolica/early_gpio.c @@ -6,6 +6,7 @@ /* GPIO pins used by coreboot should be initialized in bootblock */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { + PAD_GPO(GPIO_70, HIGH), }; void mainboard_program_early_gpios(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd398e64b1bcb46834e1b0f446cdf407825f7db8 Gerrit-Change-Number: 50188 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/amd/cezanne: Add an function to select eSPI channel
by Bao Zheng (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50187 to review the following change. Change subject: [WIP]soc/amd/cezanne: Add an function to select eSPI channel ...................................................................... [WIP]soc/amd/cezanne: Add an function to select eSPI channel Cezanne got two eSPI channels. eSPI0 shares pins with SPI. eSPI1 shares with LPC. To select the channel, the IOMUX registers about these pins are needed to be set. Change-Id: Ic110971051a25ab129608b80f8bd3395397e74ae Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50187/1 diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index dd096e0..6ab91c6 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -1,13 +1,56 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/pci_ops.h> #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> #include <amdblocks/lpc.h> #include <amdblocks/smbus.h> #include <console/console.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <soc/gpio.h> #include <soc/uart.h> +void fch_espi_channel_sel(uint8_t channel) +{ + uint32_t dword; + uint8_t byte; + + struct soc_amd_gpio espi_mux_chan0[] = { + PAD_NF(GPIO_86, LPC_SMI_L, PULL_NONE), + PAD_NF(GPIO_104, LAD0, PULL_NONE), + PAD_NF(GPIO_105, LAD1, PULL_NONE), + PAD_NF(GPIO_106, LAD2, PULL_NONE), + PAD_NF(GPIO_107, LAD3, PULL_NONE), + PAD_NF(GPIO_108, LDRQ0_L, PULL_NONE), + }; + + struct soc_amd_gpio espi_mux_chan1[] = { + PAD_NF (GPIO_30, ESPI_CS_L, PULL_NONE), + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), + }; + + if (channel == 0) { + program_gpios(espi_mux_chan0, ARRAY_SIZE(espi_mux_chan0)); + byte = pm_read8(0x92); + byte &= ~1; + pm_write8(0x92, byte); + dword = pm_read32(0x74); + dword &= ~(3 << 10); + pm_write32(0x74, dword); + } else { + program_gpios(espi_mux_chan1, ARRAY_SIZE(espi_mux_chan1)); + /* Dedicate alert pin */ + dword = pci_read_config32(SOC_LPC_DEV, 0x74); + dword &= ~(3 << 2 | 3 << 9); + dword |= 1 << 9; + pci_write_config32(SOC_LPC_DEV, 0x74, dword); + } +} /* Before console init */ void fch_pre_init(void) { diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index d57fbfe..c9b9aaa 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -56,4 +56,6 @@ void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); +void fch_espi_channel_sel(unsigned char channel); + #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic110971051a25ab129608b80f8bd3395397e74ae Gerrit-Change-Number: 50187 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage
by Bao Zheng (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49929 to look at the new patch set (#9). Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage ...................................................................... soc/amd/cezanne: Enable early LPC support in bootblock stage Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/early_fch.c A src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h 5 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/49929/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/49929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Gerrit-Change-Number: 49929 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mainboards: Drop PWRS from GNVS
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Lance Zhao, Jason Glenesk, Damien Zammit, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49352 ) Change subject: [WIP] mainboards: Drop PWRS from GNVS ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49352/comment/4937a025_7241ce6b PS8, Line 11: whether plugged on the charger or not. Does any SMI handler need to access PWRS? -- To view, visit https://review.coreboot.org/c/coreboot/+/49352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Gerrit-Change-Number: 49352 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 09:41:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboards: Drop PWRS from GNVS
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Lance Zhao, Jason Glenesk, Damien Zammit, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49352 ) Change subject: [WIP] mainboards: Drop PWRS from GNVS ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > I agree with this change about drop PWRS, that shall be done by platform but not soc. […] We already had this extra name in GNVS -- To view, visit https://review.coreboot.org/c/coreboot/+/49352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Gerrit-Change-Number: 49352 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 09:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Ronak Kanabar (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Nico Huber, Maulik V Vaghela, Paul Menzel, Subrata Banik, Aamir Bohra. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 11: (2 comments) File src/drivers/intel/fsp2_0/Kconfig.debug_blob: https://review.coreboot.org/c/coreboot/+/45905/comment/75c76d28_6f76fa09 PS5, Line 46: using new header 'FirmwareVersionInfo.h'. > Um, I was assuming that the options have prompts on purpose. If not, […] hi, i am confused here about the automatic detection how you are proposing here. can you please help me understand method you are suggesting File src/drivers/intel/fsp2_0/Kconfig.debug_blob: https://review.coreboot.org/c/coreboot/+/45905/comment/ed04cded_242e3079 PS10, Line 36: config DISPLAY_FSP_VERSION_INFO : bool "Display Firmware Ingredient Version Information" : help : Select this option to display Firmware version information. : : config DISPLAY_FSP_VERSION_INFO_2 : bool "Display firmware version information using FirmwareVersionInfo.h" > I just learned that the respective option is selected by platform code. […] yes i got your point on that removed prompt -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 09:33:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove useless comments in "includes" lines
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50186 ) Change subject: src: Remove useless comments in "includes" lines ...................................................................... src: Remove useless comments in "includes" lines Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/armv7/arch/mmio.h M src/drivers/intel/dptf/chip.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/raminit.c M src/lib/ramtest.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/lippert/frontrunner-af/sema.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/soc/nvidia/tegra124/include/soc/gpio.h M src/southbridge/amd/cimx/sb800/SBPLATFORM.h 11 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50186/1 diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index 173a0a3..45868b5 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -7,7 +7,7 @@ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ -#include <arch/cache.h> /* for dmb() */ +#include <arch/cache.h> #include <endian.h> #include <stdint.h> diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index db4c3ae..5408d9e 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -4,7 +4,7 @@ #define _DRIVERS_INTEL_DPTF_CHIP_H_ #include <acpi/acpigen_dptf.h> -#include <timer.h> /* for MSECS_PER_SEC */ +#include <timer.h> #define DPTF_PASSIVE(src, tgt, tmp, prd) \ {.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)} diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index c452f0b..23eadfa 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -9,7 +9,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/mma.h> -#include <soc/pm.h> /* chip_power_state */ +#include <soc/pm.h> struct romstage_params { uint32_t fsp_version; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dd08d77..4c468e5 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -8,7 +8,7 @@ #include <cpu/x86/smm.h> #include <fsp/romstage.h> #include <fsp/util.h> -#include <lib.h> /* hexdump */ +#include <lib.h> #include <string.h> #include <timestamp.h> diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 224393f..45178a7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -1,5 +1,5 @@ #include <stdint.h> -#include <lib.h> /* Prototypes */ +#include <lib.h> #include <console/console.h> #include <device/mmio.h> diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 88ba111..4b6f9a1 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -3,7 +3,7 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 8664560..d3d81fd 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -2,7 +2,7 @@ #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> /* src/include/gpio.h */ +#include <gpio.h> #include <spd_bin.h> #include <variant/gpio.h> #include <amdblocks/dimm_spd.h> diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index fb8e6ef..e80cc12 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -4,7 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <delay.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> #include <Porting.h> #include <AGESA.h> diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 3ce84a4..d43e6a1 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -2,7 +2,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ +#include <OEM.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/soc/nvidia/tegra124/include/soc/gpio.h b/src/soc/nvidia/tegra124/include/soc/gpio.h index 6b66a98..48601dd 100644 --- a/src/soc/nvidia/tegra124/include/soc/gpio.h +++ b/src/soc/nvidia/tegra124/include/soc/gpio.h @@ -4,7 +4,7 @@ #define __SOC_NVIDIA_TEGRA124_GPIO_H__ #include <soc/nvidia/tegra/gpio.h> -#include <soc/pinmux.h> /* for pinmux constants in GPIO macro */ +#include <soc/pinmux.h> /* GPIO index constants. */ diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 99c7323..7600886 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -44,8 +44,8 @@ #include <SBDEF.h> #include <AMDSBLIB.h> #include <SBSUBFUN.h> -#include "platform_cfg.h" /* mainboard specific configuration */ -#include <OEM.h> /* platform default configuration */ +#include "platform_cfg.h" +#include <OEM.h> #include <AMD.h> //------------------------------------------------------------------------------------------------------------------------// -- To view, visit https://review.coreboot.org/c/coreboot/+/50186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Gerrit-Change-Number: 50186 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/gma.c: Add missing `break` in switch
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50141 ) Change subject: soc/intel/broadwell/gma.c: Add missing `break` in switch ...................................................................... soc/intel/broadwell/gma.c: Add missing `break` in switch Otherwise, the `GT_CDCLK_675` case falls through and exits early. Change-Id: Icb979f8a980e1a1e1c712c5d9bc8d94c90376b7f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50141 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jacob Garber <jgarber1(a)ualberta.ca> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/gma.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Jacob Garber: Looks good to me, approved diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 6556dd4..45d1833 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -476,6 +476,7 @@ dpdiv = 338; reg_em4 = 8; reg_em5 = 225; + break; default: return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb979f8a980e1a1e1c712c5d9bc8d94c90376b7f Gerrit-Change-Number: 50141 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50017 ) Change subject: soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size ...................................................................... soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size From the output of 'objdump -x dram.elf', the DRAM blob needs 222K memory, but currently only 208K is reserved for it. Since MT8192 has 1MB SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Asurada booted successfully BRANCH=none Cq-Depend: chrome-internal:3568265 Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8192/include/soc/memlayout.ld 1 file changed, 10 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 2a21dd6..6f964f2 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -12,7 +12,7 @@ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) #define DRAM_INIT_CODE(addr, size) \ - REGION(dram_init_code, addr, size, 4) + REGION(dram_init_code, addr, size, 64K) #define DRAM_DMA(addr, size) \ REGION(dram_dma, addr, size, 4K) \ @@ -40,11 +40,16 @@ SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ BOOTBLOCK(0x00201000, 64K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) - DRAM_INIT_CODE(0x00240000, 208K) - PRERAM_CBFS_CACHE(0x00274000, 48K) - SRAM_L2C_END(0x00280000) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 252K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x00250000, 256K) + PRERAM_CBFS_CACHE(0x00290000, 48K) + SRAM_L2C_END(0x00300000) DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) -- To view, visit https://review.coreboot.org/c/coreboot/+/50017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Gerrit-Change-Number: 50017 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/i82801ix: Factor out common `acpi_fill_madt`
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50027 ) Change subject: sb/intel/i82801ix: Factor out common `acpi_fill_madt` ...................................................................... sb/intel/i82801ix: Factor out common `acpi_fill_madt` It is the same for all three mainboards. Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/roda/rk9/acpi_tables.c M src/southbridge/intel/i82801ix/Makefile.inc A src/southbridge/intel/i82801ix/madt.c 5 files changed, 36 insertions(+), 91 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 9e0ae85..862f7f4 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ioapic.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> #include <soc/nvs.h> void mainboard_fill_gnvs(struct global_nvs *gnvs) @@ -14,30 +11,3 @@ /* Temperature at which OS will throttle CPU */ gnvs->tpsv = 90; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - return current; -} diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 9e0ae85..862f7f4 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ioapic.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> #include <soc/nvs.h> void mainboard_fill_gnvs(struct global_nvs *gnvs) @@ -14,30 +11,3 @@ /* Temperature at which OS will throttle CPU */ gnvs->tpsv = 90; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - return current; -} diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 41b83c5..10deb02 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ioapic.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> #include <soc/nvs.h> void mainboard_fill_gnvs(struct global_nvs *gnvs) @@ -14,31 +11,3 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - - return current; -} diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 8eabd49..dada885 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -24,6 +24,10 @@ smm-y += smihandler.c +ifneq ($(CONFIG_BOARD_EMULATION_QEMU_X86_Q35),y) +ramstage-y += madt.c +endif + ifeq ($(CONFIG_SMM_ASEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c new file mode 100644 index 0000000..f3a7da5 --- /dev/null +++ b/src/southbridge/intel/i82801ix/madt.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + return current; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/50027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237 Gerrit-Change-Number: 50027 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021