coreboot-gerrit February 2021

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Wayne3 Wang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50103 ) Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/google/volteer/variants/drobit/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50103/comment/1beca48e_7a6a7dc7 PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > Yes, you need to modify the config.star. I had updated the setting of TBT pcie rp0 and rp1, and add the Cq-Depend: chrome-internal:3581043 for the config.star. May i know how to set the Cq-Depend on the chrome internal CL for this CL? https://chrome-internal-review.googlesource.com/c/chromeos/project/volteer/… -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 3 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Feb 2021 12:30:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/baytrail,braswell: Drop TOLM from GNVS
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50121 ) Change subject: soc/intel/baytrail,braswell: Drop TOLM from GNVS ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/braswell/acpi/southcluster.asl: https://review.coreboot.org/c/coreboot/+/50121/comment/f99b516e_8a7d3526 PS2, Line 149: /* PCI Memory Region (Top of memory-0xfeafffff) */ > Yes, comment looks bogus. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Gerrit-Change-Number: 50121 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Feb 2021 12:22:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel: Add wake source fields in GNVS
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50193 ) Change subject: sb/intel: Add wake source fields in GNVS ...................................................................... sb/intel: Add wake source fields in GNVS For the moment, these are not really used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/include/soc/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/include/soc/nvs.h M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/include/soc/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/include/soc/nvs.h 12 files changed, 41 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/50193/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55..25dcfe0 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Offset (0xb2), XHCI, 8, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 969d592..1c33b0c 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -97,7 +97,11 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd12[65]; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; + u8 rsvd12[57]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u32 cbmc; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 1e3889b..a3b15b6 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -101,4 +101,6 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index b2a6baa..933921c 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -98,6 +98,10 @@ u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index d2af885..f408a8c 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -103,4 +103,7 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 2d4980b..3c9aac9 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -98,6 +98,10 @@ u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index d2af885..264b52a 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -103,4 +103,6 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 4325a8c..54c4a2c 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -97,6 +97,10 @@ u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 949da74..46c6f4f 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Offset (0xb2), XHCI, 8, CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 5ce88a6..03897cd 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -100,6 +100,10 @@ u8 xhci; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 979e084..1b06beb 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -93,6 +93,9 @@ Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer + + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 17ded13..7db206e 100644 --- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -73,6 +73,10 @@ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Gerrit-Change-Number: 50193 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail,braswell: Sync PCI memory region in ASL
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50192 ) Change subject: soc/intel/baytrail,braswell: Sync PCI memory region in ASL ...................................................................... soc/intel/baytrail,braswell: Sync PCI memory region in ASL Baytrail had (only) occurence of DwordMemory vs DWordMemory. Braswell one had bogus comments about the PCI memory range. The actual region details are dynamically filled in _CRS. Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/braswell/acpi/southcluster.asl 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/50192/1 diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 8c715d3..75f2486 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -143,7 +143,7 @@ 0x00000000,,, LMEM) /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ - DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, PMEM) diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index d74647e..8fa95ef 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -144,11 +144,11 @@ 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000, 0x00200000,,, LMEM) - /* PCI Memory Region (Top of memory-0xfeafffff) */ + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, - 0x00100000,,, PMEM) + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, -- To view, visit https://review.coreboot.org/c/coreboot/+/50192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Gerrit-Change-Number: 50192 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] ACPI: Add acpi_reset_gnvs_for_wake()
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held. Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50004 to look at the new patch set (#3). Change subject: [WIP] ACPI: Add acpi_reset_gnvs_for_wake() ...................................................................... [WIP] ACPI: Add acpi_reset_gnvs_for_wake() Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/gnvs.c M src/include/acpi/acpi_gnvs.h M src/soc/amd/common/block/acpi/pm_state.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/ramstage.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi_wake_source.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c 19 files changed, 47 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50004/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Gerrit-Change-Number: 50004 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/baytrail,braswell: Drop TOLM from GNVS
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50121 to look at the new patch set (#4). Change subject: soc/intel/baytrail,braswell: Drop TOLM from GNVS ...................................................................... soc/intel/baytrail,braswell: Drop TOLM from GNVS It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/northcluster.c 8 files changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/50121/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Gerrit-Change-Number: 50121 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Wayne3 Wang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Wayne3 Wang, Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Hello build bot (Jenkins), Ariel Chang, Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50103 to look at the new patch set (#3). Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/50103/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 3 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Ronak Kanabar (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Nico Huber, Maulik V Vaghela, Paul Menzel, Subrata Banik, Aamir Bohra. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 12: (4 comments) File src/drivers/intel/fsp2_0/Kconfig.debug_blob: https://review.coreboot.org/c/coreboot/+/45905/comment/9896387c_be97938e PS5, Line 46: using new header 'FirmwareVersionInfo.h'. > why not use structure size itself i believe that the difference between FVI1 and FIV2 so you can kno […] @Subrata both headers files will not be present at same time. string of both struct is different. File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/45905/comment/d459d3cf_6550a92d PS11, Line 244: #if > move to col 0, no need for tab Done https://review.coreboot.org/c/coreboot/+/45905/comment/26aba40f_4fa2180b PS11, Line 246: #elif CONFIG(DISPLAY_FSP_VERSION_INFO_2) > same Done https://review.coreboot.org/c/coreboot/+/45905/comment/a85e2a55_83fa169b PS11, Line 248: #endif > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 12:09:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Wayne3 Wang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Wayne3 Wang, Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Hello build bot (Jenkins), Ariel Chang, Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50103 to look at the new patch set (#2). Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/50103/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 2 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi/acpi.h: Add MADT's MULTIPROCESSOR_WAKEUP
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50191 ) Change subject: acpi/acpi.h: Add MADT's MULTIPROCESSOR_WAKEUP ...................................................................... acpi/acpi.h: Add MADT's MULTIPROCESSOR_WAKEUP ACPI 6.4 adds Multiprocessor Wakeup. Change-Id: I999d43c9c1d6928fcf4cc3620b28a69d5319c30e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/50191/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fa24902..c313985 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -492,7 +492,8 @@ GIC_MSI_FRAME, /* GIC MSI Frame */ GICR, /* GIC Redistributor */ GIC_ITS, /* Interrupt Translation Service */ - /* 0x10-0x7f: Reserved */ + MULTIPROCESSOR_WAKEUP, /* Multiprocessor Wakeup */ + /* 0x11-0x7f: Reserved */ /* 0x80-0xff: Reserved for OEM use */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999d43c9c1d6928fcf4cc3620b28a69d5319c30e Gerrit-Change-Number: 50191 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021