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Change subject: mb/google/poppy/romstage.c: Solve lint-001 error
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49926/comment/30b9e02c_7d1108e0
PS3, Line 17: TEST = Build Google poppy
> This change should be reproducible: with BUILD_TIMELESS=1, the resulting coreboot. […]
Will perform this test.
Have just performed this test. Generated binaries remains equal.
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Change subject: console/vtxprintf.c: Correct code style
......................................................................
Patch Set 2:
(1 comment)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/49960/comment/8adf51eb_fbecd2a4
PS1, Line 41: printk(BIOS_DEBUG, "BS: " ENV_STRING " times (exec / console): total (unknown) / "
> The old version was following the Coding Style: https://doc.coreboot.org/coding_style. […]
Thanks for pointing to this paragraph.
This file should remain unchanged.
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Hello build bot (Jenkins), Nico Huber, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49960
to look at the new patch set (#2).
Change subject: console/vtxprintf.c: Correct code style
......................................................................
console/vtxprintf.c: Correct code style
Revise the following aspects to follow coreboot's coding style:
- Drop braces for single-statement condition.
- Use same indent for switch and case.
- Trailing statements on next line.
BUG = N/A
TEST = Build Compulab Intense-PC with secure oprom enabled
Change-Id: Ibb200bf7dd1ef7632aa4e1213bce72d9165560c9
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/console/vtxprintf.c
1 file changed, 21 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49960/2
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Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
......................................................................
Patch Set 11:
(1 comment)
File src/drivers/intel/fsp2_0/Kconfig.debug_blob:
https://review.coreboot.org/c/coreboot/+/45905/comment/5ab4751a_d03d1a98
PS5, Line 46: using new header 'FirmwareVersionInfo.h'.
> hi, i am confused here about the automatic detection how you are proposing here. […]
why not use structure size itself i believe that the difference between FVI1 and FIV2 so you can know the delta without any new Kconfig and use your 'C' logic to handle those delta ?
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Change subject: soc/intel/skylake: Simplify PEG port configuration
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50045/comment/e9708966_10236b53
PS3, Line 9: This configuration duplicates FSP defaults.
We do not want to rely on FSP defaults. They can be changed via BCT, or could change after an update.
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Change subject: src: Remove useless comments in "includes" lines
......................................................................
Patch Set 1: Code-Review+2
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Change subject: [WIP]soc/amd/cezanne: Add an function to select eSPI channel
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/early_fch.c:
https://review.coreboot.org/c/coreboot/+/50187/comment/1e8c1c63_2b2a804a
PS1, Line 29: PAD_NF (GPIO_30, ESPI_CS_L, PULL_NONE),
space prohibited between function name and open parenthesis '('
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Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/volteer/variants/drobit/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/50103/comment/1be76477_b00c9d0e
PS1, Line 63: device ref tbt_pcie_rp0 on end
: device ref tbt_pcie_rp1 on end
> I rewrite the CBI value of the system from 814206 to 814203. […]
Yes, you need to modify the config.star.
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