coreboot-gerrit February 2021

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Change in coreboot[master]: sb/intel/common/rcba.h: Guard RCBAx macro parameters
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50035 ) Change subject: sb/intel/common/rcba.h: Guard RCBAx macro parameters ...................................................................... sb/intel/common/rcba.h: Guard RCBAx macro parameters Add brackets around the parameters to avoid operation order problems. Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/common/rcba.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 51c4046..712a477 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -11,10 +11,10 @@ #define RCBA 0xf0 #define RCBA_ENABLE 0x01 -#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) -#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) -#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x))) +#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x)))) +#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) +#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x)))) +#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + (x)))) #define RCBA_AND_OR(bits, x, and, or) \ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) -- To view, visit https://review.coreboot.org/c/coreboot/+/50035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007 Gerrit-Change-Number: 50035 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CA...
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50161 ) Change subject: soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLE ...................................................................... soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLE Change-Id: I15a1c17e870b04cc1238b54e4f69c227c877ca09 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50161 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/skylake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f06ef72..7401d5e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,7 +32,6 @@ select HAVE_FSP_LOGO_SUPPORT select HAVE_INTEL_FSP_REPO select INTEL_CAR_NEM_ENHANCED - select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/50161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15a1c17e870b04cc1238b54e4f69c227c877ca09 Gerrit-Change-Number: 50161 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50160 ) Change subject: src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection ...................................................................... src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection CPU_INTEL_COMMON_SMM is already selected in cpu/intel/common/Kconfig file. Also remove duplicated 'CPU_INTEL_COMMON'. Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/xeon_sp/Kconfig 3 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 24ef8b3..7ad103d 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -35,7 +35,6 @@ select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM - select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 3d56758..a14be36 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -11,7 +11,6 @@ select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select SET_IA32_FC_LOCK_BIT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION @@ -37,7 +36,6 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index d84a80e..7f7135e 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -61,7 +61,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR - select CPU_INTEL_COMMON_SMM select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SMM_TSEG select HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/50160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a Gerrit-Change-Number: 50160 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/name/name.c: Clean up includes
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44315 ) Change subject: cpu/x86/name/name.c: Clean up includes ...................................................................... cpu/x86/name/name.c: Clean up includes Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/name/name.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44315/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index a7d2c70..d4f50b6 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -2,8 +2,8 @@ #include <string.h> #include <arch/cpu.h> -#include <device/device.h> #include <cpu/x86/name.h> +#include <stdint.h> void fill_processor_name(char *processor_name) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Gerrit-Change-Number: 44315 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused <cpu/x86/smm.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50171 ) Change subject: src: Remove unused <cpu/x86/smm.h> ...................................................................... src: Remove unused <cpu/x86/smm.h> Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50171 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/southcluster.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/skylake/romstage/romstage.c 4 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 67102f1..e4c2bf0 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -7,7 +7,6 @@ #include <acpi/acpi.h> #include <bootstate.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index be448f6..b9b3424 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -7,7 +7,6 @@ #include <cbmem.h> #include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <console/console.h> #include <types.h> #include <string.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index dfd7b65..38f057e 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -6,7 +6,6 @@ #include <arch/smp/mpspec.h> #include <cbmem.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <console/console.h> #include <types.h> #include <string.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index c826187..a20f279 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -4,7 +4,6 @@ #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958 Gerrit-Change-Number: 50171 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49538 ) Change subject: nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h> Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/bootblock.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 4b174cb..02b63a6 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "ironlake.h" static uint32_t encode_pciexbar_length(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Gerrit-Change-Number: 49538 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49537 ) Change subject: nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h> Also replace 'reg' with 'reg32'. Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/i945/bootblock.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index f4b4628..edb9a8d 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "i945.h" static uint32_t encode_pciexbar_length(void) @@ -27,6 +28,6 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Gerrit-Change-Number: 49537 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49541 ) Change subject: nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h> Change-Id: Ib370fc1bae017d084844eece44799676a657323b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49541 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index f15d181..aedcdd9 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -2,8 +2,8 @@ #include <arch/bootblock.h> #include <arch/mmio.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> #include "x4x.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/49541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib370fc1bae017d084844eece44799676a657323b Gerrit-Change-Number: 49541 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45815 ) Change subject: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> ...................................................................... mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/dedede/variants/drawcia/variant.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45815/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 88e9de7..321d165 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <fw_config.h> #include <sar.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Gerrit-Change-Number: 45815 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44737 ) Change subject: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include ...................................................................... soc/samsung/exynos5250/include/soc/cpu.h: Add missing include Use of 'KiB' needs <commonlib/bsd/helpers.h> Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/include/soc/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44737/1 diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index aa5a2e8..6d5c18a 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -3,6 +3,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H #define CPU_SAMSUNG_EXYNOS5250_CPU_H +#include <commonlib/bsd/helpers.h> #include <symbols.h> /* Base address registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Gerrit-Change-Number: 44737 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021