coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd: Drop PCNT from GNVS
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50119 ) Change subject: soc/amd: Drop PCNT from GNVS ...................................................................... soc/amd: Drop PCNT from GNVS It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 8 files changed, 14 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index ed2be48..ebb2bcd 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -384,6 +384,10 @@ acpigen_pop_len(); } + + acpigen_write_scope("\\"); + acpigen_write_name_integer("PCNT", logical_cores); + acpigen_pop_len(); } unsigned long southbridge_write_acpi_tables(const struct device *device, @@ -398,9 +402,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); } static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index e1b7498..294d89f 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -36,6 +36,7 @@ * Processor Object */ /* These devices are created at runtime */ +External (\PCNT, IntObj) External (\_SB.C000, DeviceObj) External (\_SB.C001, DeviceObj) External (\_SB.C002, DeviceObj) diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 9d3f381..31d375c 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - PCNT, 8, // 0x00 - Processor Count + , 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index f10fbdd..b8945ff 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -14,7 +14,7 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t lids; /* 0x01 - LID State */ uint8_t pwrs; /* 0x02 - AC Power State */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 19add66..ae2de67 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -152,6 +152,10 @@ acpigen_write_processor(cpu, 0, 0); acpigen_pop_len(); } + + acpigen_write_scope("\\"); + acpigen_write_name_integer("PCNT", cores); + acpigen_pop_len(); } unsigned long southbridge_write_acpi_tables(const struct device *device, @@ -166,9 +170,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); } static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index ca5f249..24b81a1 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -9,6 +9,7 @@ * Processor Object */ /* These devices are created at runtime */ +External (\PCNT, IntObj) External (\_SB.P000, DeviceObj) External (\_SB.P001, DeviceObj) External (\_SB.P002, DeviceObj) diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 7a48dd5..ce3653c 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -9,7 +9,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - PCNT, 8, // 0x00 - Processor Count + , 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index e4a158c..055d74b 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -14,7 +14,7 @@ struct __packed global_nvs { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t lids; /* 0x01 - LID State */ uint8_t pwrs; /* 0x02 - AC Power State */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c Gerrit-Change-Number: 50119 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDs
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50099 ) Change subject: mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDs ...................................................................... mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDs Enable Acoustic noise mitigation for magolor and set slew rate to 1/8 which is calibrated value for the board. BUG=b:178678267 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/50099 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 78d5dde..23932c3 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -71,6 +71,12 @@ register "tcc_offset" = "15" # TCC of 90C + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/50099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea Gerrit-Change-Number: 50099 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Config PlatformDebugConsent
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50108 ) Change subject: soc/intel/elkhartlake: Config PlatformDebugConsent ...................................................................... soc/intel/elkhartlake: Config PlatformDebugConsent UPD PlatformDebugConsent field is not configured. The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not used. Use this config value for PlatformDebugConsent. BUG= N/A TEST= Build Intel Elkhart Lake Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/elkhartlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 0fa8451..50add6e 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -22,6 +22,9 @@ soc_memory_init_params(m_cfg, config); + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027 Gerrit-Change-Number: 50108 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/asan.c: Update SPDX license
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50109 ) Change subject: lib/asan.c: Update SPDX license ...................................................................... lib/asan.c: Update SPDX license lint-000-license-headers reports error. The SPDX identifier contains GPL-2.0 Update the identifier to GPL-2.0-only. BUG = N/A TEST = Build Intel Elkhart Lake Change-Id: If49fd014f14b481163bca6cd3131139b6d95c6d8 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/asan.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/lib/asan.c b/src/lib/asan.c index cf91111..9493b3b 100644 --- a/src/lib/asan.c +++ b/src/lib/asan.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Address sanitizer support. -- To view, visit https://review.coreboot.org/c/coreboot/+/50109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49fd014f14b481163bca6cd3131139b6d95c6d8 Gerrit-Change-Number: 50109 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49988 ) Change subject: soc/intel/common/sata: Add support for Cannon Lake SATA (HALO) ...................................................................... soc/intel/common/sata: Add support for Cannon Lake SATA (HALO) Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller in supported device table. Bug=N/A TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully completed Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142 Signed-off-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 71c023f..2a1cfb2 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -32,6 +32,7 @@ PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, PCI_DEVICE_ID_INTEL_CNP_H_SATA, + PCI_DEVICE_ID_INTEL_CNP_H_HALO_SATA, PCI_DEVICE_ID_INTEL_CNP_LP_SATA, PCI_DEVICE_ID_INTEL_ICP_U_SATA, PCI_DEVICE_ID_INTEL_CMP_SATA, -- To view, visit https://review.coreboot.org/c/coreboot/+/49988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142 Gerrit-Change-Number: 49988 Gerrit-PatchSet: 2 Gerrit-Owner: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev ID
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49987 ) Change subject: include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev ID ...................................................................... include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev ID Add SATA controller ID for Cannon Lake PCH-H Mobile HALO (see document number: 571182) Add SPDX license header Bug=N/A TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully completed Change-Id: Ic7e6ace2a24b4278b04caa58be907d38f4d117cd Signed-off-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 45f3092..62524a3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __DEVICE_PCI_IDS_H__ #define __DEVICE_PCI_IDS_H__ @@ -3369,6 +3370,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7 #define PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA 0x282a #define PCI_DEVICE_ID_INTEL_CNP_H_SATA 0xa352 +#define PCI_DEVICE_ID_INTEL_CNP_H_HALO_SATA 0xa353 #define PCI_DEVICE_ID_INTEL_CNP_LP_SATA 0x9dd3 #define PCI_DEVICE_ID_INTEL_ICP_U_SATA 0x34d3 #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 -- To view, visit https://review.coreboot.org/c/coreboot/+/49987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7e6ace2a24b4278b04caa58be907d38f4d117cd Gerrit-Change-Number: 49987 Gerrit-PatchSet: 2 Gerrit-Owner: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: console/console.h: Move get_console_loglevel() declaration
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50083 ) Change subject: console/console.h: Move get_console_loglevel() declaration ...................................................................... console/console.h: Move get_console_loglevel() declaration If for a stage __CONSOLE_ENABLE__ is 0, then there would be no prototype for a get_console_loglevel() definition. Change-Id: I805078921a5cc1506685f8aada3af5c5241260b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50083 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/console/console.h 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/include/console/console.h b/src/include/console/console.h index a96eb15..d06b5b3 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -28,6 +28,19 @@ */ void die_notify(void); +#if CONFIG(CONSOLE_OVERRIDE_LOGLEVEL) +/* + * This function should be implemented at mainboard level. + * The returned value will _replace_ the loglevel value; + */ +int get_console_loglevel(void); +#else +static inline int get_console_loglevel(void) +{ + return CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +} +#endif + #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \ (ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \ @@ -48,19 +61,6 @@ #define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args) enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; - -#if CONFIG(CONSOLE_OVERRIDE_LOGLEVEL) -/* - * This function should be implemented at mainboard level. - * The returned value will _replace_ the loglevel value; - */ -int get_console_loglevel(void); -#else -static inline int get_console_loglevel(void) -{ - return CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -} -#endif #else static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I805078921a5cc1506685f8aada3af5c5241260b7 Gerrit-Change-Number: 50083 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/security/cbnt: Fix bootblock size
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50082 ) Change subject: drivers/security/cbnt: Fix bootblock size ...................................................................... drivers/security/cbnt: Fix bootblock size Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/security/intel/cbnt/Kconfig 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index bb907f1..c439dca 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -57,4 +57,11 @@ bool default y +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xc000 if FIXED_BOOTBLOCK_SIZE + help + This matches the IBB size used for CBnT. Adjust this to the + used CBnT settings. + endif # BOARD_OCP_DELTALAKE diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig index f13f6ec..e5830b7 100644 --- a/src/security/intel/cbnt/Kconfig +++ b/src/security/intel/cbnt/Kconfig @@ -6,6 +6,8 @@ depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE #depends on PLATFORM_HAS_DRAM_CLEAR select INTEL_TXT + # With CBnT the bootblock is set up as a CBnT IBB and needs a fixed size + select FIXED_BOOTBLOCK_SIZE help Enables Intel Converged Bootguard and Trusted Execution Technology Support. This will enable one to add a Key Manifest (KM) and a Boot -- To view, visit https://review.coreboot.org/c/coreboot/+/50082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Gerrit-Change-Number: 50082 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/mp_init.c: Print out the microcode revision of APs
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49840 ) Change subject: cpu/x86/mp_init.c: Print out the microcode revision of APs ...................................................................... cpu/x86/mp_init.c: Print out the microcode revision of APs It is useful to know if MCU have been applied successfully. On the start of MP init lines similar to: "AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed. The example is taken from the log of an ocp/deltalake. Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/mp_init.c 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c691c48..cca6093 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -196,8 +196,12 @@ /* Fix up APIC id with reality. */ info->cpu->path.apic.apic_id = lapicid(); - printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu, - info->cpu->path.apic.apic_id); + if (cpu_is_intel()) + printk(BIOS_INFO, "AP: slot %d apic_id %x, MCU rev: 0x%08x\n", cpu, + info->cpu->path.apic.apic_id, get_current_microcode_rev()); + else + printk(BIOS_INFO, "AP: slot %d apic_id %x\n", cpu, + info->cpu->path.apic.apic_id); /* Walk the flight plan */ ap_do_flight_plan(); -- To view, visit https://review.coreboot.org/c/coreboot/+/49840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a Gerrit-Change-Number: 49840 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/microcode: Reuse existing function to read MCU revision
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49839 ) Change subject: cpu/intel/microcode: Reuse existing function to read MCU revision ...................................................................... cpu/intel/microcode: Reuse existing function to read MCU revision Change-Id: If198fa68c0a29f46906151e667d7b00e2a3ab00d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49839 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 9d6d28b..8673990 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -123,8 +123,8 @@ size_t microcode_len; u32 eax; u32 pf, rev, sig, update_size; - unsigned int x86_model, x86_family; msr_t msr; + struct cpuinfo_x86 c; if (ucode_updates) return ucode_updates; @@ -133,19 +133,13 @@ if (ucode_updates == NULL) return NULL; - /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, msr); + rev = read_microcode_rev(); eax = cpuid_eax(1); - msr = rdmsr(IA32_BIOS_SIGN_ID); - rev = msr.hi; - x86_model = (eax >> 4) & 0x0f; - x86_family = (eax >> 8) & 0x0f; + get_fms(&c, eax); sig = eax; pf = 0; - if ((x86_model >= 5) || (x86_family > 6)) { + if ((c.x86_model >= 5) || (c.x86 > 6)) { msr = rdmsr(IA32_PLATFORM_ID); pf = 1 << ((msr.hi >> 18) & 7); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If198fa68c0a29f46906151e667d7b00e2a3ab00d Gerrit-Change-Number: 49839 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021