coreboot-gerrit February 2021

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Change in coreboot[master]: treewide [Kconfig]: Remove useless comment
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50185 ) Change subject: treewide [Kconfig]: Remove useless comment ...................................................................... treewide [Kconfig]: Remove useless comment Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/external/U-Boot/Kconfig M payloads/libpayload/arch/arm/Kconfig M payloads/libpayload/arch/arm64/Kconfig M payloads/libpayload/arch/x86/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/veyron/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 21 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/50185/1 diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index a2bc512..9e51ae1 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -1,6 +1,6 @@ if PAYLOAD_UBOOT -config PAYLOAD_SPECIFIC_OPTIONS # dummy +config PAYLOAD_SPECIFIC_OPTIONS def_bool y select PAYLOAD_IS_FLAT_BINARY diff --git a/payloads/libpayload/arch/arm/Kconfig b/payloads/libpayload/arch/arm/Kconfig index b5a2be5..acaf167 100644 --- a/payloads/libpayload/arch/arm/Kconfig +++ b/payloads/libpayload/arch/arm/Kconfig @@ -28,7 +28,7 @@ if ARCH_ARM -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN diff --git a/payloads/libpayload/arch/arm64/Kconfig b/payloads/libpayload/arch/arm64/Kconfig index 439d27b..18f3770 100644 --- a/payloads/libpayload/arch/arm64/Kconfig +++ b/payloads/libpayload/arch/arm64/Kconfig @@ -28,7 +28,7 @@ if ARCH_ARM64 -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index 05cf58b..f590d58 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -28,7 +28,7 @@ if ARCH_X86 -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN select IO_ADDRESS_SPACE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index aafe110..cc24833 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -5,7 +5,7 @@ if CPU_INTEL_SLOT_1 -config SLOT_SPECIFIC_OPTIONS # dummy +config SLOT_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 1b930de..5b6ae7f 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_441 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX select MMX diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3ce106a..0848d26 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_LGA775 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 32eedb6..50eb7e3 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_M -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 176ae9e..7b08699 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_MPGA604 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X select MMX diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 894df57..48df9ca 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -2,7 +2,7 @@ if BOARD_AMD_PADMELON -config BOARD_SPECIFIC_OPTIONS # dummy +config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_STONEYRIDGE select AMD_APU_PKG_FP4 diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 1d3496c..97444d8 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards +config BOARD_GOOGLE_VEYRON def_bool n if BOARD_GOOGLE_VEYRON diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index e07691a..d222e2e 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_E7505 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 256b088..58942f0 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_GM45 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 456193a..23369e7 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_I945 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index b1863ef..ad134f2 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_PINEVIEW -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 32e85d3..711340d 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_X4X -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index d0fbc49..06162775 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -8,7 +8,7 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy +config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 6280f3a..b3b844f 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -11,7 +11,7 @@ if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy +config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 06ac5c6..21816e5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -8,7 +8,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index cea0efe..f172bf1 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -5,7 +5,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ad3c00..a9a2f5b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -5,7 +5,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/50185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Gerrit-Change-Number: 50185 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*: Get rid of custom microcode caching
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49897 ) Change subject: soc/intel/*: Get rid of custom microcode caching ...................................................................... soc/intel/*: Get rid of custom microcode caching Get rid of custom microcode caching in MPinit and SGX code and use the caching introduced in intel_microcode_find() instead. Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/xeon_sp/cpx/cpu.c 7 files changed, 13 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index ff6cbec..fd6a82a 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -9,11 +9,10 @@ #include <device/device.h> /* Parallel MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { - intel_microcode_load_unlocked(microcode_patch); + const void *patch = intel_microcode_find(); + intel_microcode_load_unlocked(patch); /* Setup MTRRs based on physical address size. */ x86_setup_mtrrs_with_detect(); @@ -32,7 +31,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { - *microcode = microcode_patch; + *microcode = intel_microcode_find(); *parallel = !intel_ht_supported(); } @@ -98,8 +97,6 @@ void mp_init_cpus(struct bus *cpu_bus) { - microcode_patch = intel_microcode_find(); - if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 44552f5..dd2aeef 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -123,8 +123,6 @@ } /* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -149,8 +147,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; + *microcode = intel_microcode_find(); *parallel = !intel_ht_supported(); } @@ -160,6 +157,7 @@ smm_relocate(); /* After SMM relocation a 2nd microcode load is required. */ + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 31099fd..ef04d39 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -466,8 +466,6 @@ } /* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -492,8 +490,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; + *microcode = intel_microcode_find(); *parallel = !intel_ht_supported(); } @@ -503,6 +500,7 @@ smm_relocate(); /* After SMM relocation a 2nd microcode load is required. */ + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); } diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 4fd2074..8f8cd06 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -15,8 +15,6 @@ #include <intelblocks/msr.h> #include <soc/cpu.h> -static const void *microcode_patch; - /* SoC override function */ __weak void soc_core_init(struct device *dev) { @@ -31,6 +29,8 @@ static void init_one_cpu(struct device *dev) { soc_core_init(dev); + + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); } @@ -105,17 +105,6 @@ } /* - * Function to get the microcode patch pointer. Use this function to avoid - * reading the microcode patch from the boot media. init_cpus() would - * initialize microcode_patch global variable to point to microcode patch - * in boot media and this function can be used to access the pointer. - */ -const void *intel_mp_current_microcode(void) -{ - return microcode_patch; -} - -/* * MP Init callback function(get_microcode_info) to find the Microcode at * Pre MP Init phase. This function is common among all SOCs and thus its in * Common CPU block. @@ -125,7 +114,7 @@ */ void get_microcode_info(const void **microcode, int *parallel) { - *microcode = intel_mp_current_microcode(); + *microcode = intel_microcode_find(); *parallel = 1; } @@ -151,7 +140,7 @@ if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; - microcode_patch = intel_microcode_find(); + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); init_cpus(); diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 7dc85df..9038dd5 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -54,14 +54,6 @@ int get_cpu_count(void); /* - * Function to get the microcode patch pointer. Use this function to avoid - * reading the microcode patch from the boot media. init_cpus() would - * initialize microcode_patch global variable to point to microcode patch - * in boot media and this function can be used to access the pointer. - */ -const void *intel_mp_current_microcode(void); - -/* * MP Init callback function(get_microcode_info) to find the Microcode at * Pre MP Init phase. This function is common among all SOCs and thus its in * Common CPU block. diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 336ed54..b5c8944 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -224,7 +224,7 @@ * loads and to prevent simultaneous load attempts to the same core. */ if (!intel_ht_sibling()) { - const void *microcode_patch = intel_mp_current_microcode(); + const void *microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); } diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 4dea1a4..be01fc0 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -58,15 +58,10 @@ */ void get_microcode_info(const void **microcode, int *parallel) { - *microcode = intel_mp_current_microcode(); + *microcode = intel_microcode_find(); *parallel = 0; } -const void *intel_mp_current_microcode(void) -{ - return microcode_patch; -} - static void each_cpu_init(struct device *cpu) { msr_t msr; -- To view, visit https://review.coreboot.org/c/coreboot/+/49897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Gerrit-Change-Number: 49897 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/oprom/include/x86emu/fpu_regs.h: Fix lint error
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49938 ) Change subject: device/oprom/include/x86emu/fpu_regs.h: Fix lint error ...................................................................... device/oprom/include/x86emu/fpu_regs.h: Fix lint error `make lint` reports errors and warnings Solve the next errors: - SPACE_BEFORE_TAB - SPACING BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: Ic7062e07a76bf95fe8e2e849f1d14342c9081a23 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49938 Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/oprom/include/x86emu/fpu_regs.h 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/device/oprom/include/x86emu/fpu_regs.h b/src/device/oprom/include/x86emu/fpu_regs.h index a872e19..10fe9f9 100644 --- a/src/device/oprom/include/x86emu/fpu_regs.h +++ b/src/device/oprom/include/x86emu/fpu_regs.h @@ -1,8 +1,8 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) 1996-1999 SciTech Software, Inc. * Copyright (C) David Mosberger-Tang * Copyright (C) 1999 Egbert Eich * @@ -103,13 +103,13 @@ #endif /* X86_FPU_SUPPORT */ #if CONFIG(X86EMU_DEBUG) -# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ - DECODE_PRINTF(t[(mod<<3)+(rh)]); -# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ - DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +# define DECODE_PRINTINSTR32(t, mod, rh, rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]) +# define DECODE_PRINTINSTR256(t, mod, rh, rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]) #else -# define DECODE_PRINTINSTR32(t,mod,rh,rl) -# define DECODE_PRINTINSTR256(t,mod,rh,rl) +# define DECODE_PRINTINSTR32(t, mod, rh, rl) +# define DECODE_PRINTINSTR256(t, mod, rh, rl) #endif #endif /* __X86EMU_FPU_REGS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7062e07a76bf95fe8e2e849f1d14342c9081a23 Gerrit-Change-Number: 49938 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CAR
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49877 ) Change subject: drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CAR ...................................................................... drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CAR TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 551b4b9..14d9742 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -113,7 +113,7 @@ config FSP_CAR bool default n - select NO_CBFS_MCACHE + select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT help Use FSP APIs to initialize & Tear Down the Cache-As-Ram -- To view, visit https://review.coreboot.org/c/coreboot/+/49877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30560149eeaec62af4c8a982815618be5546531c Gerrit-Change-Number: 49877 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Use native CAR teardown
by Arthur Heymans (Code Review) 01 Feb '21

01 Feb '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48467 ) Change subject: soc/intel/xeon_sp: Use native CAR teardown ...................................................................... soc/intel/xeon_sp: Use native CAR teardown This cleans up the postcar frame setup, which now gets used instead of just going with TempRamExit MTRR's (Note that CPU init overwrites them anyway). TESTED on ocp/deltalake. Change-Id: I756c2d479fef859a460696300422f08013a300f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/memmap.c 2 files changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48467/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 369d474..ce92ed5 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -47,6 +47,14 @@ says this needs to be 256KiB, but practice show this needs to be a lot more. +config NO_FSP_TEMP_RAM_EXIT + bool + default y + +config INTEL_CAR_NEM + bool + default y + config CPU_MICROCODE_CBFS_LOC hex default 0xfff0fdc0 diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index cd81754..0af0ad2 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -29,17 +29,22 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t cbmem_base; + size_t cbmem_size; + /* Try account for the CBMEM region currently used and for future use */ + cbmem_get_region((void **)&cbmem_base, &cbmem_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16 * MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK); + printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); + /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ + cbmem_base -= 4 * MiB; + cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); + + /* Align the top to make sure we don't use too many MTRR's */ + cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB); + + postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ if (CONFIG(TSEG_STAGE_CACHE)) postcar_enable_tseg_cache(pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/48467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I756c2d479fef859a460696300422f08013a300f1 Gerrit-Change-Number: 48467 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Use coreboot postcar with FSP-T
by Arthur Heymans (Code Review) 01 Feb '21

01 Feb '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48466 ) Change subject: drivers/intel/fsp2_0: Use coreboot postcar with FSP-T ...................................................................... drivers/intel/fsp2_0: Use coreboot postcar with FSP-T Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are a few reasons to do this: - Tearing down CAR is easy. - Having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - This removes the need to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/common/block/cpu/Makefile.inc 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48466/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 96ae282..d38a292 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,6 +117,13 @@ help Use FSP APIs to initialize & Tear Down the Cache-As-Ram +config NO_FSP_TEMP_RAM_EXIT + bool + depends on FSP_CAR + help + Select this on a platform where you want to use FSP-T but use + coreboot code to tear down CAR. + config FSP_M_XIP bool default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 298198d..3fbfda1 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -29,7 +29,9 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +ifneq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y) postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +endif postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c postcar-y += hand_off_block.c diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 7692076..5131658 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_FSP_CAR),y) bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU)+= car/cache_as_ram_fsp.S +ifeq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y) +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car.S +else postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car_fsp.S +endif else bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S -- To view, visit https://review.coreboot.org/c/coreboot/+/48466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Gerrit-Change-Number: 48466 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Wayne3 Wang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50103 ) Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/volteer/variants/drobit/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50103/comment/4e494898_bff00bee PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > Do you check the FW_CONFIG in the CBI? The bit 0-3 should be set to 0011b. […] I rewrite the CBI value of the system from 814206 to 814203. The issue of system hangs cannot be duplicated. For this result, should i modify the config.star of drobit? But it seems to be not match with the hardware design. https://review.coreboot.org/c/coreboot/+/50103/comment/36f25e71_d912d6ef PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > Do you check the FW_CONFIG in the CBI? The bit 0-3 should be set to 0011b. […] I rewrite the CBI value of the system from 814206 to 814203. The issue of system hangs cannot be duplicated. For this result, should i modify the config.star of drobit? But it seems to be not match with the hardware design. -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 1 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Feb 2021 08:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ACPI: Move PICM and _PIC declarations
by Lance Zhao (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Kyösti Mälkki, Patrick Rudolph, Piotr Król, Jason Glenesk, Anjaneya "Reddy" Chagam, Michał Żygowski, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49905 ) Change subject: [WIP] ACPI: Move PICM and _PIC declarations ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Yes the _PIC and PICM is almost identical. However I don't think acpigen_extern.asl will expect a method within that. Also according to ACPI spec, _PIC is optional, then we can't have coreboot always have _PIC for every combination of platform. The following from ACPI 6.3 spec page 341 Notice that calling this method is optional for OSPM. -- To view, visit https://review.coreboot.org/c/coreboot/+/49905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Gerrit-Change-Number: 49905 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 07:46:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Zhuohao Lee (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Wayne3 Wang, Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50103 ) Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/volteer/variants/drobit/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50103/comment/3543eef9_3f7d6c54 PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > I try to add the "probe DB_USB USB4_GEN3" to tbt_pcie_rp0 and tbt_pcie_rp1. […] Do you check the FW_CONFIG in the CBI? The bit 0-3 should be set to 0011b. Please refer to baseboard/devicetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 1 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 06:56:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mainboards: Drop PWRS from GNVS
by Lance Zhao (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Angel Pons, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Damien Zammit, Marshall Dawson, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Alexander Couzens, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49352 ) Change subject: [WIP] mainboards: Drop PWRS from GNVS ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: I agree with this change about drop PWRS, that shall be done by platform but not soc. But again do we have better option other than dsdt_top.asl? That will make a system without anything to do with AC/DC power state will have an extra name? -- To view, visit https://review.coreboot.org/c/coreboot/+/49352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Gerrit-Change-Number: 49352 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 06:41:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021