coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/siemens/mc_apl1: do UART pad configuration at board-level
by Uwe Poeche (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Michael Niewöhner. Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49442 ) Change subject: mb/siemens/mc_apl1: do UART pad configuration at board-level ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: start siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/49442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Gerrit-Change-Number: 49442 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 05:58:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
by Wayne3 Wang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50103 ) Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/volteer/variants/drobit/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50103/comment/f03515a8_dc7f0916 PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > Adding the `probe` statement(s) would probably be safest, but if all drobit SKUs will have USB4 then […] I try to add the "probe DB_USB USB4_GEN3" to tbt_pcie_rp0 and tbt_pcie_rp1. But the system hangs in recovery page that can be duplicated again. Modify >>> device domain 0 on device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 end device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 end device ref i2c0 on Modify <<< I check the all drobit SKUs that will have the design of USB4. Maybe we can keep the settings? https://review.coreboot.org/c/coreboot/+/50103/comment/185172e6_04386632 PS1, Line 63: device ref tbt_pcie_rp0 on end : device ref tbt_pcie_rp1 on end > Adding the `probe` statement(s) would probably be safest, but if all drobit SKUs will have USB4 then […] I try to add the "probe DB_USB USB4_GEN3" to tbt_pcie_rp0 and tbt_pcie_rp1. But the system hangs in recovery page that can be duplicated again. Modify >>> device domain 0 on device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 end device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 end device ref i2c0 on Modify <<< I check the all drobit SKUs that will have the design of USB4. Maybe we can keep the settings? -- To view, visit https://review.coreboot.org/c/coreboot/+/50103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Gerrit-Change-Number: 50103 Gerrit-PatchSet: 1 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 05:57:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Add configurable value for ConfigTdpLevel
by Derek Huang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50104 ) Change subject: soc/intel/tgl: Add configurable value for ConfigTdpLevel ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50104/comment/c402e3a2_4d69361f PS1, Line 17: > Needs 'Signed-off-by' tag Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Gerrit-Change-Number: 50104 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Feb 2021 03:49:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Add configurable value for ConfigTdpLevel
by Derek Huang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Patrick Rudolph. Hello build bot (Jenkins), Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50104 to look at the new patch set (#4). Change subject: soc/intel/tgl: Add configurable value for ConfigTdpLevel ...................................................................... soc/intel/tgl: Add configurable value for ConfigTdpLevel According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> --- M src/soc/intel/tigerlake/chip.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/50104/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Gerrit-Change-Number: 50104 Gerrit-PatchSet: 4 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Change cTDP level to level 2 (15W)
by Derek Huang (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50105 to look at the new patch set (#2). Change subject: mb/google/volteer: Change cTDP level to level 2 (15W) ...................................................................... mb/google/volteer: Change cTDP level to level 2 (15W) Change the cTDP level from base (28W) to level 2 (15W) to align with PL1. The change is for UP3 variants, UP4 variants should keep base TDP level (9W) which already align with PL1. Refer to Tigerlake TDP specifications (doc #575683, table 4-2) for details Change-Id: I4420a6a2e463b0a6bd7eb4b81f6a4fb975895ea3 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/drobit/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb M src/soc/intel/tigerlake/romstage/fsp_params.c 8 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50105/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4420a6a2e463b0a6bd7eb4b81f6a4fb975895ea3 Gerrit-Change-Number: 50105 Gerrit-PatchSet: 2 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size
by Hung-Te Lin (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50017 ) Change subject: soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Gerrit-Change-Number: 50017 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 02:54:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: force 3GB dram
by Xi Chen (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Xi Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50019 to look at the new patch set (#2). Change subject: TEST-ONLY: soc/mediatek/mt8192: force 3GB dram ...................................................................... TEST-ONLY: soc/mediatek/mt8192: force 3GB dram Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I1a1a00bd3fb78cf248cee92b3261574072bca58f --- M src/soc/mediatek/mt8192/emi.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/50019/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a1a00bd3fb78cf248cee92b3261574072bca58f Gerrit-Change-Number: 50019 Gerrit-PatchSet: 2 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Remove unused <boardid.h>
by Hung-Te Lin (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: HAOUAS Elyes. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50183 ) Change subject: src: Remove unused <boardid.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Gerrit-Change-Number: 50183 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 01 Feb 2021 02:03:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/copano: support regular/numpad touchpad
by Zhuohao Lee (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50129 ) Change subject: mb/google/volteer/variant/copano: support regular/numpad touchpad ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Logic looks okay to me. […] Yes. We need two device nodes and use the FW_CONFIG to switch it at runtime. -- To view, visit https://review.coreboot.org/c/coreboot/+/50129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Gerrit-Change-Number: 50129 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 01 Feb 2021 01:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021