coreboot-gerrit February 2021

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Change in coreboot[master]: arch/x86/smbios: Add Number Of Power Cords field to be overriden
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50015 ) Change subject: arch/x86/smbios: Add Number Of Power Cords field to be overriden ...................................................................... arch/x86/smbios: Add Number Of Power Cords field to be overriden For SMBIOS type 3, add function to override number of power cords Tested=Exectute dmidecode -t 3 to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu(a)wiwynn.com> Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/smbios.c M src/arch/x86/smbios_defaults.c M src/include/smbios.h 3 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index b3e1c13..8c595ff 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -609,6 +609,7 @@ t->thermal_state = SMBIOS_STATE_SAFE; t->_type = smbios_mainboard_enclosure_type(); t->security_status = SMBIOS_STATE_SAFE; + t->number_of_power_cords = smbios_chassis_power_cords(); t->asset_tag_number = smbios_add_string(t->eos, smbios_mainboard_asset_tag()); t->version = smbios_add_string(t->eos, smbios_chassis_version()); t->serial_number = smbios_add_string(t->eos, smbios_chassis_serial_number()); diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 4d8883f3..3d26bbb 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -143,3 +143,8 @@ { return ""; } + +__weak u8 smbios_chassis_power_cords(void) +{ + return 1; +} diff --git a/src/include/smbios.h b/src/include/smbios.h index 2f63aac..5cbd3c3 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -54,6 +54,7 @@ const char *smbios_chassis_version(void); const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +u8 smbios_chassis_power_cords(void); /* This string could be filled late in payload. */ void smbios_type0_bios_version(uintptr_t address); -- To view, visit https://review.coreboot.org/c/coreboot/+/50015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0 Gerrit-Change-Number: 50015 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Calculate TSEG limit from registers
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46991 ) Change subject: nb/intel/haswell: Calculate TSEG limit from registers ...................................................................... nb/intel/haswell: Calculate TSEG limit from registers Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46991/1 diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 02d120b..c19cfec 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,13 +4,13 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt_register.h> +#include <types.h> #include "haswell.h" @@ -19,9 +19,9 @@ return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); } -static size_t northbridge_get_tseg_size(void) +static uintptr_t northbridge_get_tseg_limit(void) { - return CONFIG_SMM_TSEG_SIZE; + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB); } union dpr_register txt_get_chipset_dpr(void) @@ -62,7 +62,9 @@ void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_limit(); + + *size -= *start; } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/46991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Gerrit-Change-Number: 46991 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use correct port mask for LPT-LP
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47035 ) Change subject: sb/intel/lynxpoint: Use correct port mask for LPT-LP ...................................................................... sb/intel/lynxpoint: Use correct port mask for LPT-LP Lynxpoint LP only has 4 SATA ports. Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47035/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 167f4df..f4ad6cd 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -12,6 +12,12 @@ #include "iobp.h" #include "pch.h" +#if CONFIG(INTEL_LYNXPOINT_LP) +#define SATA_PORT_MASK 0x0f +#else +#define SATA_PORT_MASK 0x3f +#endif + typedef struct southbridge_intel_lynxpoint_config config_t; static inline u32 sir_read(struct device *dev, int idx) @@ -95,7 +101,7 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ - pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); + pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -121,7 +127,7 @@ /* SATA Initialization register */ reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0x3f) << 24; + reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); @@ -241,7 +247,7 @@ * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8); + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365 Gerrit-Change-Number: 47035 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Initiate peripheral buses
by EricR Lai (Code Review) 01 Feb '21

01 Feb '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49007 ) Change subject: mb/google/brya: Initiate peripheral buses ...................................................................... mb/google/brya: Initiate peripheral buses Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 107 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..96e0a9d 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,113 @@ device lapic 0 on end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_ENABLED, + }" + + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_ENABLED, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -30,7 +137,6 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/49007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Gerrit-Change-Number: 49007 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboard
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50096 ) Change subject: mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboard ...................................................................... mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboard This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each individual board to select it. TEST=Verified that timeless build does not result in any changes. Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name 2 files changed, 2 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index e529c7a..3217d07 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -31,6 +31,7 @@ select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG + select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE select HAVE_SPD_IN_CBFS @@ -39,7 +40,7 @@ config CHROMEOS bool default y - select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 292ab3e..5bb1794 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -3,24 +3,20 @@ config BOARD_GOOGLE_DELBIN bool "-> Delbin" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_ELDRID bool "-> Eldrid" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_HALVOR bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM config BOARD_GOOGLE_LINDAR bool "-> Lindar" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 @@ -28,38 +24,32 @@ config BOARD_GOOGLE_MALEFOR bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_TODOR bool "-> Todor" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM config BOARD_GOOGLE_TRONDO bool "-> Trondo" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA - select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER2 bool "-> Volteer2" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA - select SOC_INTEL_CSE_LITE_SKU select DRIVERS_GENESYSLOGIC_GL9755 select DRIVER_I2C_TPM_ACPI @@ -68,33 +58,27 @@ bool "-> Volteer2_Ti50" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA - select SOC_INTEL_CSE_LITE_SKU select DRIVERS_GENESYSLOGIC_GL9755 select DRIVER_I2C_TPM_ACPI config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_DROBIT bool "-> Drobit" select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_COPANO bool "-> Copano" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU -- To view, visit https://review.coreboot.org/c/coreboot/+/50096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Gerrit-Change-Number: 50096 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Drop boldar variant
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50095 ) Change subject: mb/google/volteer: Drop boldar variant ...................................................................... mb/google/volteer: Drop boldar variant This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name D src/mainboard/google/volteer/variants/boldar/include/variant/ec.h D src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h D src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc D src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt D src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt D src/mainboard/google/volteer/variants/boldar/overridetree.cb 8 files changed, 0 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index cfe8dde..e529c7a 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -104,7 +104,6 @@ default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL - default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI default "Voema" if BOARD_GOOGLE_VOEMA default "Drobit" if BOARD_GOOGLE_DROBIT @@ -146,7 +145,6 @@ default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL - default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI default "voema" if BOARD_GOOGLE_VOEMA default "drobit" if BOARD_GOOGLE_DROBIT diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 2b0a089..292ab3e 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -77,11 +77,6 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU -config BOARD_GOOGLE_BOLDAR - bool "-> Boldar" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM - config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h b/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h deleted file mode 100644 index 7a2a6ff..0000000 --- a/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __VARIANT_EC_H__ -#define __VARIANT_EC_H__ - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h deleted file mode 100644 index b5fa8c5..0000000 --- a/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -/* Memory configuration board straps */ -/* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_D15 - -#endif diff --git a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc deleted file mode 100644 index ed894fe..0000000 --- a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! - -SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) Parts = EMPTY diff --git a/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt deleted file mode 100644 index 2e3fcbc..0000000 --- a/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt +++ /dev/null @@ -1,2 +0,0 @@ -DRAM Part Name ID to assign -EMPTY 0 (0000) diff --git a/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt deleted file mode 100644 index 7f7204c..0000000 --- a/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt +++ /dev/null @@ -1 +0,0 @@ -EMPTY diff --git a/src/mainboard/google/volteer/variants/boldar/overridetree.cb b/src/mainboard/google/volteer/variants/boldar/overridetree.cb deleted file mode 100644 index 32204c5..0000000 --- a/src/mainboard/google/volteer/variants/boldar/overridetree.cb +++ /dev/null @@ -1,6 +0,0 @@ -chip soc/intel/tigerlake - - device domain 0 on - end - -end -- To view, visit https://review.coreboot.org/c/coreboot/+/50095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Gerrit-Change-Number: 50095 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Change EC -> PCH wake pin to GPP_F17
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50084 ) Change subject: mb/google/brya: Change EC -> PCH wake pin to GPP_F17 ...................................................................... mb/google/brya: Change EC -> PCH wake pin to GPP_F17 A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/gpio.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index f91dcc8..bbc59a7 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -241,7 +241,7 @@ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ @@ -342,8 +342,8 @@ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> NC */ + PAD_NC(GPD2, NONE), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 6f41718..2024e48 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -8,7 +8,7 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK +/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ +#define GPE_EC_WAKE GPE0_DW2_17 #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Gerrit-Change-Number: 50084 Gerrit-PatchSet: 3 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "mb/google/hatch/dratini: Describe the privacy_gpio"
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50044 ) Change subject: Revert "mb/google/hatch/dratini: Describe the privacy_gpio" ...................................................................... Revert "mb/google/hatch/dratini: Describe the privacy_gpio" This reverts commit f41645c34d8b22a3d887abd56138ae794fc2dfa5. In Dragonair, during the MP stage, one of the resistors needed for this functionality has been removed. This results in the privacy-switch not readable back by the system. BUG=b:178458332 Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/dratini/overridetree.cb 2 files changed, 0 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 32591b8..712a918 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -16,8 +16,6 @@ PAD_NC(GPP_A19, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), - /* D4 : Camera Privacy Status */ - PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 3605196..6176fc6 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -72,19 +72,6 @@ device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - # The Linux Kernel does not allow an inverted BOTH_EDGE irq - # So we need to use GpioIO() instead of GpioInt() - # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt - register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" - device usb 2.6 on end - end - end - end - end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/50044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625 Gerrit-Change-Number: 50044 Gerrit-PatchSet: 5 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Lance Zhao (Code Review) 01 Feb '21

01 Feb '21

Attention is currently required from: Michael Niewöhner. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: The advantage of current implementation is people porting coreboot to different hardware not need to care about the detail mux setting just as simple as which uart port is using is good enough. And FSP will always program the GPIO pad base on uart selection base on FSP upd setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 26 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 01 Feb 2021 08:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp
by Patrick Georgi (Code Review) 01 Feb '21

01 Feb '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49235 ) Change subject: ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp ...................................................................... ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp 1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.c M src/drivers/ipmi/ocp/ipmi_ocp.h A src/drivers/ipmi/ocp/ipmi_ocp_romstage.c M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/ramstage.c M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/ipmi.c M src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c 14 files changed, 150 insertions(+), 167 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc index 8291f82..c77ee4a 100644 --- a/src/drivers/ipmi/ocp/Makefile.inc +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -1 +1,4 @@ ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c +ifeq ($(CONFIG_IPMI_OCP),y) +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c +endif diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c index 07628ee..ee38bb0 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.c +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -12,6 +12,7 @@ #include <device/device.h> #include <device/pnp.h> #include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <intelblocks/cpulib.h> #include <string.h> #include <types.h> @@ -115,6 +116,30 @@ printk(BIOS_ERR, "IPMI BMC set param 2 processor info failed\n"); } +static enum cb_err ipmi_set_ppin(struct device *dev) +{ + int ret; + struct ipmi_rsp rsp; + struct ppin_req req = {0}; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + if (CONFIG_MAX_SOCKET > 1) { + req.cpu1_lo = xeon_sp_ppin[1].lo; + req.cpu1_hi = xeon_sp_ppin[1].hi; + } + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) &req, sizeof(req), (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + printk(BIOS_DEBUG, "IPMI: %s command success\n", __func__); + return CB_SUCCESS; +} + static void ipmi_ocp_init(struct device *dev) { /* Add OCP specific IPMI command */ @@ -126,6 +151,8 @@ /* Send processor information */ ipmi_set_processor_information(dev); + if (CONFIG(OCP_DMI)) + ipmi_set_ppin(dev); } static void ipmi_set_resources(struct device *dev) diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h index 96b0086..0c9f452 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.h +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -7,6 +7,12 @@ #include <cpu/x86/name.h> #include "drivers/ipmi/ipmi_kcs.h" +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 +#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 + #define IPMI_NETFN_OEM_COMMON 0x36 #define IPMI_BMC_SET_PROCESSOR_INFORMATION 0x10 #define IPMI_BMC_GET_PROCESSOR_INFORMATION 0x11 @@ -14,6 +20,12 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce +#define CMOS_BIT (1 << 1) +#define VALID_BIT (1 << 7) +#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= ~(CMOS_BIT | VALID_BIT)) +#define SET_CMOS_AND_VALID_BIT(x) ((x) |= (CMOS_BIT | VALID_BIT)) +#define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) + struct ipmi_processor_info_req { uint8_t manufacturer_id[3]; uint8_t index; @@ -33,4 +45,22 @@ char revision[2]; } __packed; +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; + +struct boot_order { + uint8_t boot_mode; + uint8_t boot_dev0; + uint8_t boot_dev1; + uint8_t boot_dev2; + uint8_t boot_dev3; + uint8_t boot_dev4; +} __packed; + +enum cb_err ipmi_set_post_start(const int port); +enum cb_err ipmi_set_cmos_clear(void); #endif diff --git a/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c new file mode 100644 index 0000000..8e43d8d --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_ocp_romstage.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> + +#include "ipmi_ocp.h" + +enum cb_err ipmi_set_post_start(const int port) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(port, IPMI_NETFN_OEM, 0x0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, + sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + if (ret != sizeof(rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return CB_ERR; + } + + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); + return CB_SUCCESS; +} + +enum cb_err ipmi_set_cmos_clear(void) +{ + int ret; + + struct ipmi_oem_rsp { + struct ipmi_rsp resp; + struct boot_order data; + } __packed; + + struct ipmi_oem_rsp rsp; + struct boot_order req; + + /* IPMI OEM get bios boot order command to check if the valid bit and + the CMOS clear bit are both set from the response BootMode byte. */ + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_GET_BIOS_BOOT_ORDER, + NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + if (!IS_CMOS_AND_VALID_BIT(rsp.data.boot_mode)) { + req = rsp.data; + SET_CMOS_AND_VALID_BIT(req.boot_mode); + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_SET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + printk(BIOS_INFO, "IPMI CMOS clear requested because CMOS data is invalid.\n"); + + return CB_SUCCESS; + } + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index 7adbcf2..9022215 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -3,30 +3,13 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> #include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/vpd/vpd.h> #include <string.h> #include "ipmi.h" #include "vpd.h" -enum cb_err ipmi_set_ppin(struct ppin_req *req) -{ - int ret; - struct ipmi_rsp rsp; - - ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, - (const unsigned char *) req, sizeof(*req), - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", - __func__, ret, rsp.completion_code); - return CB_ERR; - } - - return CB_SUCCESS; -} - enum cb_err ipmi_get_pcie_config(uint8_t *pcie_config) { int ret; @@ -75,29 +58,6 @@ return CB_SUCCESS; } -enum cb_err ipmi_set_post_start(const int port) -{ - int ret; - struct ipmi_rsp rsp; - - ret = ipmi_kcs_message(port, IPMI_NETFN_OEM, 0x0, - IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, - sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", - __func__, ret, rsp.completion_code); - return CB_ERR; - } - if (ret != sizeof(rsp)) { - printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); - return CB_ERR; - } - - printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); - return CB_SUCCESS; -} - void init_frb2_wdt(void) { uint8_t enable; @@ -135,51 +95,3 @@ ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); } } - -enum cb_err ipmi_set_cmos_clear(void) -{ - int ret; - - struct ipmi_oem_rsp { - struct ipmi_rsp resp; - struct boot_order data; - } __packed; - - struct ipmi_oem_rsp rsp; - struct boot_order req; - - /* IPMI OEM get bios boot order command to check if the valid bit and - the CMOS clear bit are both set from the response BootMode byte. */ - - ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, - IPMI_OEM_GET_BIOS_BOOT_ORDER, - NULL, 0, - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", - __func__, ret, rsp.resp.completion_code); - return CB_ERR; - } - - if (!IS_CMOS_AND_VALID_BIT(rsp.data.boot_mode)) { - req = rsp.data; - SET_CMOS_AND_VALID_BIT(req.boot_mode); - ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, - IPMI_OEM_SET_BIOS_BOOT_ORDER, - (const unsigned char *) &req, sizeof(req), - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", - __func__, ret, rsp.resp.completion_code); - return CB_ERR; - } - - printk(BIOS_INFO, "IPMI CMOS clear requested because CMOS data is invalid.\n"); - - return CB_SUCCESS; - } - - return CB_SUCCESS; -} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index 440a505..269fc03 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -5,19 +5,9 @@ #include <stdint.h> -#define IPMI_NETFN_OEM 0x30 -#define IPMI_OEM_SET_PPIN 0x77 -#define IPMI_OEM_GET_PCIE_CONFIG 0xf4 -#define IPMI_OEM_GET_BOARD_ID 0x37 -#define IPMI_BMC_SET_POST_START 0x73 -#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 -#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 +#define IPMI_OEM_GET_PCIE_CONFIG 0xf4 +#define IPMI_OEM_GET_BOARD_ID 0x37 -#define CMOS_BIT (1 << 1) -#define VALID_BIT (1 << 7) -#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= ~(CMOS_BIT | VALID_BIT)) -#define SET_CMOS_AND_VALID_BIT(x) ((x) |= (CMOS_BIT | VALID_BIT)) -#define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) enum config_type { PCIE_CONFIG_UNKNOWN = 0x0, @@ -27,26 +17,8 @@ PCIE_CONFIG_D = 0x4, }; -struct ppin_req { - uint32_t cpu0_lo; - uint32_t cpu0_hi; - uint32_t cpu1_lo; - uint32_t cpu1_hi; -} __packed; - -struct boot_order { - uint8_t boot_mode; - uint8_t boot_dev0; - uint8_t boot_dev1; - uint8_t boot_dev2; - uint8_t boot_dev3; - uint8_t boot_dev4; -} __packed; - -enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); enum cb_err ipmi_get_slot_id(uint8_t *slot_id); -enum cb_err ipmi_set_post_start(const int port); void init_frb2_wdt(void); -enum cb_err ipmi_set_cmos_clear(void); + #endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 4a3e385..40810b6 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -353,13 +353,6 @@ static void mainboard_final(void *chip_info) { - struct ppin_req req = {0}; - - req.cpu0_lo = xeon_sp_ppin[0].lo; - req.cpu0_hi = xeon_sp_ppin[0].hi; - /* Set PPIN to BMC */ - if (ipmi_set_ppin(&req) != CB_SUCCESS) - printk(BIOS_ERR, "ipmi_set_ppin failed\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 9b182a21..0a7ecf1 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/vpd/vpd.h> #include <fsp/api.h> #include <FspmUpd.h> diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 67c1fa9..2ead76d 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -8,6 +8,7 @@ select HAVE_ACPI_TABLES select IPMI_KCS select IPMI_KCS_ROMSTAGE + select IPMI_OCP select MAINBOARD_USES_FSP2_0 select OCP_DMI select PARALLEL_MP_AP_WORK diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 488f677..833bb20 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -76,6 +76,9 @@ register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "90" end + chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c index 0cdf110..74f96fe 100644 --- a/src/mainboard/ocp/tiogapass/ipmi.c +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -3,29 +3,13 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> #include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/vpd/vpd.h> #include <string.h> #include "ipmi.h" #include "vpd.h" -void ipmi_set_ppin(struct ppin_req *req) -{ - int ret; - struct ipmi_rsp rsp; - - ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, - (const unsigned char *) req, sizeof(*req), - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", - __func__, ret, rsp.completion_code); - return; - } - printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n"); -} - void init_frb2_wdt(void) { char val[VPD_LEN]; diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h index 798f312..93101c2 100644 --- a/src/mainboard/ocp/tiogapass/ipmi.h +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -4,17 +4,5 @@ #define TIOGAPASS_IPMI_H #include <types.h> -#define IPMI_NETFN_OEM 0x30 -#define IPMI_OEM_SET_PPIN 0x77 - -/* PPIN for 2 CPU IPMI request */ -struct ppin_req { - uint32_t cpu0_lo; - uint32_t cpu0_hi; - uint32_t cpu1_lo; - uint32_t cpu1_hi; -} __packed; -/* Send CPU0 and CPU1 PPIN to BMC */ -void ipmi_set_ppin(struct ppin_req *req); void init_frb2_wdt(void); #endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 29148d1..df77205 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -7,8 +7,6 @@ #include <soc/ramstage.h> #include <soc/lewisburg_pch_gpio_defs.h> -#include "ipmi.h" - extern struct fru_info_str fru_strings; static const struct port_information SMBIOS_type8_info[] = { @@ -185,14 +183,6 @@ static void mainboard_final(void *chip_info) { - struct ppin_req req; - - req.cpu0_lo = xeon_sp_ppin[0].lo; - req.cpu0_hi = xeon_sp_ppin[0].hi; - req.cpu1_lo = xeon_sp_ppin[1].lo; - req.cpu1_hi = xeon_sp_ppin[1].hi; - /* Set PPIN to BMC */ - ipmi_set_ppin(&req); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index fb2ce02..20c7466 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -3,6 +3,7 @@ #include <fsp/api.h> #include <FspmUpd.h> #include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> #include <soc/romstage.h> #include <string.h> #include <gpio.h> @@ -53,8 +54,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { /* It's better to run get BMC selftest result first */ - if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { + ipmi_set_post_start(CONFIG_BMC_KCS_BASE); init_frb2_wdt(); + } mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Gerrit-Change-Number: 49235 Gerrit-PatchSet: 7 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021