coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86/smbios_defaults.c: Default to motherboard type
by Nico Huber (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50180 ) Change subject: arch/x86/smbios_defaults.c: Default to motherboard type ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Hmmm, I'm a bit undecided. We already make the assumption that adding a single type 2 table makes sense (it doesn't always). OTOH, it shouldn't hurt to call that single board `mainboard`. If somebody really needs more accurate SMBIOS tables, the `unknown` type most probably wouldn't help either. -- To view, visit https://review.coreboot.org/c/coreboot/+/50180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1419874a0ba3f2e21568fa4b07b88f2048d10203 Gerrit-Change-Number: 50180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
by Raul Rangel (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50287 ) Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/amd/picasso/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50287/comment/4ab0534f_433b96a1 PS1, Line 75: PICASSO_ Just wondering why we have PICASSO in the name? Nothing else in this file is prefixed with the SoC name. -- To view, visit https://review.coreboot.org/c/coreboot/+/50287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a Gerrit-Change-Number: 50287 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:52:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh. Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/147728ae_7754d184 PS3, Line 236: LpmStateEnableMask > Hi Shreesh, I was referring to adding configs for external bypass, external clk and phy gate to `soc […] Yes Furquan. I updated the patch with adding 3 new configs in chip.h and using them in the fsp_params.c. I am creating another patch for updating values of these in the devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 9 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:47:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50288 ) Change subject: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: see PcdAmdFchCfgCpuControlBlkAddr in the .dec file -- To view, visit https://review.coreboot.org/c/coreboot/+/50288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Gerrit-Change-Number: 50288 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:47:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: add missing include
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50266 ) Change subject: soc/amd/common/block/acpi/pm_state: add missing include ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I think <amdblocks/acpi.h> is included and not used here : […] i'll probably do a cleanup run after cezanne is mostly working and Kyösti is done with his acpi and gnvs related work. having an unneeded include for some time shouldn't really hurt -- To view, visit https://review.coreboot.org/c/coreboot/+/50266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2 Gerrit-Change-Number: 50266 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:42:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by build bot (Jenkins) (Code Review) 04 Feb '21

04 Feb '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49766/comment/6c6e0f59_f9d66d96 PS9, Line 71: /* If external phy gating is not implemented, S0i3.3/S0i3.4/S0i2.2 are not recommended. */ line over 96 characters https://review.coreboot.org/c/coreboot/+/49766/comment/6a5e8670_272db9df PS9, Line 76: if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) || is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH))) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 9 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:42:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Shreesh Chhabbi. Hello build bot (Jenkins), Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#9). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 9 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50288 ) Change subject: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA ...................................................................... [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA This still needs to be verified on real hardware. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50288/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 4031fa0..80c3f46 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -78,7 +78,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x13) +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x10) /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Gerrit-Change-Number: 50288 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50287 ) Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option ...................................................................... soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option This was the only I/O base address in Kconfig, no board changed it and if a board changed it, it needs to make sure that it won't overlap with other I/O resources, so just use the same value as constant in the define instead of the value from Kconfig. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/iomap.h 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50287/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4989ee2..4868d84 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -263,12 +263,6 @@ Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode. -config PICASSO_ACPI_IO_BASE - hex - default 0x400 - help - Base address for the ACPI registers. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 0296c87..4031fa0 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -72,7 +72,7 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define PICASSO_ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a Gerrit-Change-Number: 50287 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/9019ad61_62d6d95c PS1, Line 19: 0x0400 > Curious why not use CONFIG_CEZANNE_ACPI_IO_BASE. 0x400 should be fine though. I don't really expect that to need to be changed and just to avoid clutter in the kconfig. this is also the only base address in the io space that is in kconfig in picasso and no board overrides that; the rest of the io base addresses are in there as defines, so this makes it more consistent. it also removes the chance to have overlapping io regions due to misconfiguration in the kconfig. i'm planning to port this change back to picasso as well https://review.coreboot.org/c/coreboot/+/50270/comment/d9c48cfd_67c0496b PS1, Line 25: 0x10 > This differs from Picasso. […] i commented on the patch you linked that that doesn't line up with what the reference code does and try to keep this closely to the reference code, since we did run into some issue on picasso due to using a value different to what the reference code did. i also opened a ticket for the ppr to have it aligned with the reference code. have a look at the values of PcdAmdFchCfgAcpiPm1EvtBlkAddr and friends in the corresponding .dec file. i probably should write a patch for picasso as well, but that one definitely needs to be tested on different hardware -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Feb 2021 20:22:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021