Attention is currently required from: Furquan Shaikh.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )
Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
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Patch Set 9:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49766/comment/147728ae_7754d184
PS3, Line 236: LpmStateEnableMask
Hi Shreesh, I was referring to adding configs for external bypass, external clk and phy gate to `soc […]
Yes Furquan. I updated the patch with adding 3 new configs in chip.h and using them in the fsp_params.c. I am creating another patch for updating values of these in the devicetree.
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