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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
......................................................................
soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/acpi.c
M src/soc/amd/picasso/include/soc/iomap.h
3 files changed, 7 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50287/2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50288
to look at the new patch set (#2).
Change subject: [UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
......................................................................
[UNTESTED] soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
This still needs to be verified on real hardware.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527
---
M src/soc/amd/picasso/include/soc/iomap.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50288/2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50050 )
Change subject: soc/intel/skylake: Move L1_substates_control to pcie_rp.h
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> Should the config name be reverted to match the UPD (PcieRpL1Substates) for consistency with other p […]
Did anything change, though. My strongest argument was that if it uses
different values, it should have a different name. If that still applies,
I'd rather update the other platforms.
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Change subject: soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges
......................................................................
Patch Set 1: Code-Review+2
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Change subject: intel: Define `RCBA_LENGTH` in Kconfig and use it
......................................................................
Patch Set 4: Code-Review+2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50180 )
Change subject: arch/x86/smbios_defaults.c: Default to motherboard type
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hmmm, I'm a bit undecided. We already make the assumption that […]
Hmmm, yes: for COMe and blade servers, we should probably be adding more than one type 2 table.
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Change subject: arch/x86/smbios_defaults.c: Default to motherboard type
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Hmmm, I'm a bit undecided. We already make the assumption that
adding a single type 2 table makes sense (it doesn't always).
OTOH, it shouldn't hurt to call that single board `mainboard`.
If somebody really needs more accurate SMBIOS tables, the
`unknown` type most probably wouldn't help either.
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Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/soc/amd/picasso/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50287/comment/4ab0534f_433b96a1
PS1, Line 75: PICASSO_
Just wondering why we have PICASSO in the name? Nothing else in this file is prefixed with the SoC name.
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Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49766/comment/147728ae_7754d184
PS3, Line 236: LpmStateEnableMask
> Hi Shreesh, I was referring to adding configs for external bypass, external clk and phy gate to `soc […]
Yes Furquan. I updated the patch with adding 3 new configs in chip.h and using them in the fsp_params.c. I am creating another patch for updating values of these in the devicetree.
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