coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tgl: Enable/Disable S0ix substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#11). Change subject: soc/intel/tgl: Enable/Disable S0ix substates ...................................................................... soc/intel/tgl: Enable/Disable S0ix substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 11 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49766 to look at the new patch set (#10). Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates S0i3.2 and S0i3.3 are applicable only if wake on voice is disabled. As per Platform Design Guide, S0i3.2 and S0i3.3 substates need to be disabled for Tigerlake. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 10 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Raul Rangel (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/b540af2f_fc2dc47c PS2, Line 25: 0x10 So in CB:41128 this was changed to 0x0c. Is the TMR_BLK only 2 bytes? -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:32:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable External Bypass, ClkGate & PhyGate
by build bot (Jenkins) (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Shreesh Chhabbi. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50290 ) Change subject: mb/google/volteer: Enable External Bypass, ClkGate & PhyGate ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/volteer/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/50290/comment/e0ec690a_06894114 PS1, Line 253: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:31:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable External Bypass, ClkGate & PhyGate
by Shreesh Chhabbi (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Shreesh Chhabbi. Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50290 to review the following change. Change subject: mb/google/volteer: Enable External Bypass, ClkGate & PhyGate ...................................................................... mb/google/volteer: Enable External Bypass, ClkGate & PhyGate Sets the soc config options for ExternalBypass, ExternalClkGate and ExternalPhyGate. These are used to enable or disable respective S0ix substates. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/50290/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index d74476a..0bbcdba 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -250,6 +250,15 @@ # Enable DPTF register "dptf_enable" = "1" + + # Enable External Bypass + register "ExternalBypass" = "1" + + # Enable External Clk Gate + register "ExternalClkGated" = "1" + + # Enable External Phy Gate + register "ExternalPhyGated" = "1" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, -- To view, visit https://review.coreboot.org/c/coreboot/+/50290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Gerrit-Change-Number: 50290 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
by Sukumar Ghorai (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 ) Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates ...................................................................... Patch Set 9: Code-Review+1 (1 comment) Patchset: PS9: @Furquan, patch Verified and working as expected. pls review the patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/49766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Gerrit-Change-Number: 49766 Gerrit-PatchSet: 9 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50270 ) Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/50270/comment/bcc3795b_69b38cd5 PS1, Line 19: 0x0400 > > Curious why not use CONFIG_CEZANNE_ACPI_IO_BASE. 0x400 should be fine though. […] dropped the CEZANNE_ part here as requested by Raul in the corresponding patch for picasso CB:50287 -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
by Raul Rangel (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50287 ) Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a Gerrit-Change-Number: 50287 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Feb 2021 21:18:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50273 to look at the new patch set (#2). Change subject: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy ...................................................................... [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy This isn't meant to be submitted in the current state. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 --- A src/mainboard/amd/majolica/dsdt.asl A src/mainboard/google/guybrush/dsdt.asl M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/include/soc/acpi.h A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 8 files changed, 121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50273/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Gerrit-Change-Number: 50273 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/fch: add ACPI I/O port setup
by Felix Held (Code Review) 04 Feb '21

04 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50270 to look at the new patch set (#2). Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup ...................................................................... soc/amd/cezanne/fch: add ACPI I/O port setup The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from the reference code, but not the PPR. I've submitted a change request for the PPR, so this mismatch might go away in the future. The case for HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends up being identical to the function in soc/amd/picasso, I'll move it to the common AMD SoC code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/50270/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f Gerrit-Change-Number: 50270 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2021