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Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50270/comment/bcc3795b_69b38cd5
PS1, Line 19: 0x0400
> > Curious why not use CONFIG_CEZANNE_ACPI_IO_BASE. 0x400 should be fine though. […]
dropped the CEZANNE_ part here as requested by Raul in the corresponding patch for picasso CB:50287
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Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50270
to look at the new patch set (#2).
Change subject: soc/amd/cezanne/fch: add ACPI I/O port setup
......................................................................
soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/cezanne/include/soc/southbridge.h
3 files changed, 69 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/50270/2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50273
to look at the new patch set (#2).
Change subject: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy
......................................................................
[WIP] soc/amd/cezanne: select ACPI support and make the compiler happy
This isn't meant to be submitted in the current state.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132
---
A src/mainboard/amd/majolica/dsdt.asl
A src/mainboard/google/guybrush/dsdt.asl
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/acpi.c
A src/soc/amd/cezanne/include/soc/acpi.h
A src/soc/amd/cezanne/include/soc/nvs.h
M src/soc/amd/cezanne/include/soc/southbridge.h
8 files changed, 121 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50273/2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50235 )
Change subject: mb/emulation/qemu: Fix SMP boot
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/qemu-x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/50235/comment/7e36e094_9baa7678
PS2, Line 48: default 4
Why did the default change?
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Change subject: soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/picasso/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/50287/comment/f389f5a3_6d6f1242
PS1, Line 75: PICASSO_
> Just wondering why we have PICASSO in the name? Nothing else in this file is prefixed with the SoC n […]
hmm, good question. let's get rid of that too
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