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Change subject: mb/google/mancomb: Add new mainboard
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Patch Set 7: Code-Review+1
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Change subject: mb/google/dedede: Modify USB 3.0 PHY parameters for galith
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50253/comment/2b83e705_b8034a52
PS2, Line 7: galith
> Do 'galith' and 'galtic' refer to the same board?
Galtic/Galnat/Galith be used the same board, create varient name use galtic
but recent Galtic/Galnat is closed
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Change subject: mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
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Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50276/comment/4e2e5537_ce68a2ed
PS1, Line 13: master
> Done
I meant "BRANCH=none", but I guess it's also fine to remove it.
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Change subject: mb/google/dedede/var/galtic: Configure I2C high and low time
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Patch Set 1: Code-Review+2
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50051 )
Change subject: acpi: Fix BERT size_t printf format error
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Patch Set 2:
This change is ready for review.
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50292 )
Change subject: soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
......................................................................
soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/include/soc/iomap.h
2 files changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/50292/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index baf3f4e..b400e1b 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -250,13 +250,6 @@
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
-config STONEYRIDGE_ACPI_IO_BASE
- hex
- default 0x400
- help
- Base address for the ACPI registers.
- This value must match the hardcoded value of AGESA.
-
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index e532f18..32618e2 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -27,7 +27,7 @@
/* I/O Ranges */
#define ACPI_SMI_CTL_PORT 0xb2
-#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define ACPI_IO_BASE 0x400
#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
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