coreboot-gerrit February 2021

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 ) Change subject: mb/intel/shadowmountain: Add the ramstage code ...................................................................... Patch Set 3: (2 comments) File src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c: https://review.coreboot.org/c/coreboot/+/49732/comment/07a93f63_25386506 PS3, Line 33: /* D15 : MEM_STRAP_3 */ : PAD_CFG_GPI(GPP_D15, NONE, DEEP), can be marked NC, only 0, 1, 2 are been used for memory straps. File src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/49732/comment/5305e4d0_e08ebd1f PS3, Line 164: /* E10 : PCH_GSPI0_H1_TPM_CS_L */ : PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), : /* E11 : PCH_GSPI0_H1_TPM_CLK */ : PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), : /* E12 : PCH_GSPIO_H1_TPM_MISO */ : PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), : /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ : PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), can be skipped , part of early gpio table. -- To view, visit https://review.coreboot.org/c/coreboot/+/49732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Gerrit-Change-Number: 49732 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 05:24:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add the romstage code
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Angel Pons, Balaji Manigandan. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49731 ) Change subject: mb/intel/shadowmountain: Add the romstage code ...................................................................... Patch Set 3: (2 comments) File src/mainboard/intel/shadowmountain/variants/baseboard/memory.c: https://review.coreboot.org/c/coreboot/+/49731/comment/b2666e15_0277b6a3 PS3, Line 58: false enable https://review.coreboot.org/c/coreboot/+/49731/comment/7d934ae1_f7048f9f PS3, Line 78: GPP_D15, unused, needs to be dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/49731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Gerrit-Change-Number: 49731 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 05:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by Aamir Bohra (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Nico Huber, Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Angel Pons, Balaji Manigandan. Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 05:09:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENH
by Sheng-Liang Pan (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49967 ) Change subject: mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENH ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49967/comment/a77b4b56_15387fa2 PS2, Line 13: TEST=emerge-volteer coreboot chromeos-bootimage > Have you tested that this change: […] 1) stylus popup while use stylus touch panel, then disappears when pen inserted. 2) wake function is normal. -- To view, visit https://review.coreboot.org/c/coreboot/+/49967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb Gerrit-Change-Number: 49967 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 04:55:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Add mediatek mt8192 dram vendor code
by Xi Chen (Code Review) 05 Feb '21

05 Feb '21

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: Add mediatek mt8192 dram vendor code ...................................................................... Add mediatek mt8192 dram vendor code Move coreboot mt8192 soc dram code to vendor folder, it's more convinient to maintain mediatek dram codes. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc M src/vendorcode/Makefile.inc A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Kconfig A src/vendorcode/mediatek/mt8192/Makefile.inc R src/vendorcode/mediatek/mt8192/dpm.c R src/vendorcode/mediatek/mt8192/dramc_ana_init_config.c R src/vendorcode/mediatek/mt8192/dramc_dig_config.c R src/vendorcode/mediatek/mt8192/dramc_dvfs.c R src/vendorcode/mediatek/mt8192/dramc_param.c R src/vendorcode/mediatek/mt8192/dramc_pi_basic_api.c R src/vendorcode/mediatek/mt8192/dramc_pi_calibration_api.c R src/vendorcode/mediatek/mt8192/dramc_pi_main.c R src/vendorcode/mediatek/mt8192/dramc_power.c R src/vendorcode/mediatek/mt8192/dramc_subsys_config.c R src/vendorcode/mediatek/mt8192/dramc_tracking.c R src/vendorcode/mediatek/mt8192/dramc_utility.c R src/vendorcode/mediatek/mt8192/emi.c R src/vendorcode/mediatek/mt8192/include/soc/dpm.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_ac_timing.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_pi_api.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_power.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_register.h R src/vendorcode/mediatek/mt8192/include/soc/dramc_register_bits_def.h R src/vendorcode/mediatek/mt8192/include/soc/emi.h R src/vendorcode/mediatek/mt8192/memory.c 29 files changed, 62 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index beadaf2..cc09262 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -16,43 +16,6 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE -config DEBUG_DRAM - bool "Output verbose DRAM related debug messages" - default y - help - This option enables additional DRAM related debug messages. - -config MT8192_DRAM_EMCP - bool - default y - help - The eMCP platform should select this option to run at different DRAM - frequencies. - -config MT8192_DRAM_DVFS - bool - default n - help - This option enables DRAM calibration with multiple frequencies (low, - medium and high frequency groups, with total 7 frequencies) for DVFS - feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, - 3200, 4266. - -config MT8192_DRAM_DVFS_LIMIT_FREQ_CNT - bool - default y - select MT8192_DRAM_DVFS - help - This options limit DRAM frequency calibration count from total 7 to 3, - other frequency will directly use the low frequency shu result. - -config MEMORY_TEST - bool - default y - help - This option enables memory basic compare test to verify the DRAM read - or write is as expected. - config DPM_DM_FIRMWARE string default "dpm.dm" diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d41a23c..972c1e9 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -28,15 +28,11 @@ romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c -romstage-y += dramc_utility.c dramc_dvfs.c dramc_tracking.c dramc_power.c -romstage-y += dramc_subsys_config.c dramc_ana_init_config.c dramc_dig_config.c -romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c mmu_operations.c -romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c @@ -48,12 +44,10 @@ ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c -ramstage-y += dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c -ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/mcu.c ramstage-y += mcupm.c @@ -97,6 +91,7 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/include $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 8ccb0d0..36a13bb 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan +subdirs-y += mediatek diff --git a/src/vendorcode/mediatek/Makefile.inc b/src/vendorcode/mediatek/Makefile.inc new file mode 100644 index 0000000..d100489 --- /dev/null +++ b/src/vendorcode/mediatek/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += mt8192 diff --git a/src/vendorcode/mediatek/mt8192/Kconfig b/src/vendorcode/mediatek/mt8192/Kconfig new file mode 100644 index 0000000..3b31953 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/Kconfig @@ -0,0 +1,40 @@ +if SOC_MEDIATEK_MT8192 + +config DEBUG_DRAM + bool "Output verbose DRAM related debug messages" + default y + help + This option enables additional DRAM related debug messages. + +config MT8192_DRAM_EMCP + bool + default y + help + The eMCP platform should select this option to run at different DRAM + frequencies. + +config MT8192_DRAM_DVFS + bool + default n + help + This option enables DRAM calibration with multiple frequencies (low, + medium and high frequency groups, with total 7 frequencies) for DVFS + feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, + 3200, 4266. + +config MT8192_DRAM_DVFS_LIMIT_FREQ_CNT + bool + default y + select MT8192_DRAM_DVFS + help + This options limit DRAM frequency calibration count from total 7 to 3, + other frequency will directly use the low frequency shu result. + +config MEMORY_TEST + bool + default y + help + This option enables memory basic compare test to verify the DRAM read + or write is as expected. + +endif diff --git a/src/vendorcode/mediatek/mt8192/Makefile.inc b/src/vendorcode/mediatek/mt8192/Makefile.inc new file mode 100644 index 0000000..20fd124 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/Makefile.inc @@ -0,0 +1,18 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) + +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c +romstage-y += dramc_utility.c dramc_dvfs.c dramc_tracking.c dramc_power.c +romstage-y += dramc_subsys_config.c dramc_ana_init_config.c dramc_dig_config.c +romstage-y += emi.c +romstage-y += memory.c dramc_param.c + +ramstage-y += dpm.c +ramstage-y += emi.c + +BL31_MAKEARGS += PLAT=mt8192 + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include +CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/include + +endif diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/vendorcode/mediatek/mt8192/dpm.c similarity index 100% rename from src/soc/mediatek/mt8192/dpm.c rename to src/vendorcode/mediatek/mt8192/dpm.c diff --git a/src/soc/mediatek/mt8192/dramc_ana_init_config.c b/src/vendorcode/mediatek/mt8192/dramc_ana_init_config.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_ana_init_config.c rename to src/vendorcode/mediatek/mt8192/dramc_ana_init_config.c diff --git a/src/soc/mediatek/mt8192/dramc_dig_config.c b/src/vendorcode/mediatek/mt8192/dramc_dig_config.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_dig_config.c rename to src/vendorcode/mediatek/mt8192/dramc_dig_config.c diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/vendorcode/mediatek/mt8192/dramc_dvfs.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_dvfs.c rename to src/vendorcode/mediatek/mt8192/dramc_dvfs.c diff --git a/src/soc/mediatek/mt8192/dramc_param.c b/src/vendorcode/mediatek/mt8192/dramc_param.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_param.c rename to src/vendorcode/mediatek/mt8192/dramc_param.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc_pi_basic_api.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_pi_basic_api.c rename to src/vendorcode/mediatek/mt8192/dramc_pi_basic_api.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8192/dramc_pi_calibration_api.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_pi_calibration_api.c rename to src/vendorcode/mediatek/mt8192/dramc_pi_calibration_api.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc_pi_main.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_pi_main.c rename to src/vendorcode/mediatek/mt8192/dramc_pi_main.c diff --git a/src/soc/mediatek/mt8192/dramc_power.c b/src/vendorcode/mediatek/mt8192/dramc_power.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_power.c rename to src/vendorcode/mediatek/mt8192/dramc_power.c diff --git a/src/soc/mediatek/mt8192/dramc_subsys_config.c b/src/vendorcode/mediatek/mt8192/dramc_subsys_config.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_subsys_config.c rename to src/vendorcode/mediatek/mt8192/dramc_subsys_config.c diff --git a/src/soc/mediatek/mt8192/dramc_tracking.c b/src/vendorcode/mediatek/mt8192/dramc_tracking.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_tracking.c rename to src/vendorcode/mediatek/mt8192/dramc_tracking.c diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/vendorcode/mediatek/mt8192/dramc_utility.c similarity index 100% rename from src/soc/mediatek/mt8192/dramc_utility.c rename to src/vendorcode/mediatek/mt8192/dramc_utility.c diff --git a/src/soc/mediatek/mt8192/emi.c b/src/vendorcode/mediatek/mt8192/emi.c similarity index 100% rename from src/soc/mediatek/mt8192/emi.c rename to src/vendorcode/mediatek/mt8192/emi.c diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/vendorcode/mediatek/mt8192/include/soc/dpm.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dpm.h rename to src/vendorcode/mediatek/mt8192/include/soc/dpm.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_ac_timing.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_ac_timing.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_param.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_pi_api.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_pi_api.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_power.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_power.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_power.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_power.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_register.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_register.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_register.h diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h b/src/vendorcode/mediatek/mt8192/include/soc/dramc_register_bits_def.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h rename to src/vendorcode/mediatek/mt8192/include/soc/dramc_register_bits_def.h diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/vendorcode/mediatek/mt8192/include/soc/emi.h similarity index 100% rename from src/soc/mediatek/mt8192/include/soc/emi.h rename to src/vendorcode/mediatek/mt8192/include/soc/emi.h diff --git a/src/soc/mediatek/mt8192/memory.c b/src/vendorcode/mediatek/mt8192/memory.c similarity index 100% rename from src/soc/mediatek/mt8192/memory.c rename to src/vendorcode/mediatek/mt8192/memory.c -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by Subrata Banik (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Nico Huber, Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Angel Pons, Balaji Manigandan, Aamir Bohra. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 04:25:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code
by Subrata Banik (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: V Sowmya, Paul Menzel, Tim Wawrzynczak, Balaji Manigandan, Aamir Bohra. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49733 ) Change subject: mb/intel/shadowmountain: Add the ASL code ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Gerrit-Change-Number: 49733 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 04:25:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by V Sowmya (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Nico Huber, Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Subrata Banik, Angel Pons, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 7: (3 comments) Patchset: PS6: > Selection of CHROMEOS seems unwarranted and should be explained in detail. I have removed the selection and will handle it from the config.<board>. File src/mainboard/intel/shadowmountain/Kconfig: https://review.coreboot.org/c/coreboot/+/49479/comment/c682f53b_91413718 PS5, Line 24: default y > If that is true, this is the first board that requires CHROMEOS […] I have removed the selection and will handle it from the config.<board> [https://review.coreboot.org/c/coreboot/+/50118] File src/mainboard/intel/shadowmountain/Kconfig: https://review.coreboot.org/c/coreboot/+/49479/comment/c575c9a1_5f7a974c PS6, Line 6: select CHROMEOS > @Sowmya, you don't need to select this by default. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 04:19:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/shadowmountain: Add the ASL code
by V Sowmya (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49733 to look at the new patch set (#4). Change subject: mb/intel/shadowmountain: Add the ASL code ...................................................................... mb/intel/shadowmountain: Add the ASL code This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e --- M src/mainboard/intel/shadowmountain/dsdt.asl 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/49733/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Gerrit-Change-Number: 49733 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code
by V Sowmya (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49732 to look at the new patch set (#3). Change subject: mb/intel/shadowmountain: Add the ramstage code ...................................................................... mb/intel/shadowmountain: Add the ramstage code This patch includes the ramstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/Makefile.inc A src/mainboard/intel/shadowmountain/ec.c A src/mainboard/intel/shadowmountain/mainboard.c A src/mainboard/intel/shadowmountain/smihandler.c M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c A src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h 11 files changed, 761 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/49732/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Gerrit-Change-Number: 49732 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2021