coreboot-gerrit February 2021

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Change in coreboot[master]: src: Remove redundant include <rules.h>
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50300 ) Change subject: src: Remove redundant include <rules.h> ...................................................................... src: Remove redundant include <rules.h> Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/romstage.c M src/drivers/intel/fsp1_1/include/fsp/util.h M src/soc/amd/common/block/psp/psp_smm.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/50300/1 diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c index 5146b0e..c7340b2 100644 --- a/src/arch/riscv/romstage.c +++ b/src/arch/riscv/romstage.c @@ -9,7 +9,6 @@ #include <arch/stages.h> #include <arch/smp/smp.h> -#include <rules.h> #include <mcall.h> void stage_entry(int hart_id, void *fdt) diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index cab867a..e67ecd1 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -3,7 +3,6 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H -#include <rules.h> #include <arch/cpu.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 7c15616..95c3e4e 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -4,7 +4,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <region_file.h> -#include <rules.h> #include <console/console.h> #include <amdblocks/psp.h> #include <soc/iomap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Gerrit-Change-Number: 50300 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Ronak Kanabar (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50299 ) Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 08:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add chain-include list of headers
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Julius Werner. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50286 ) Change subject: Documentation: Add chain-include list of headers ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: Thx File Documentation/chain-include.md: https://review.coreboot.org/c/coreboot/+/50286/comment/833c57db_a88ae72e PS1, Line 33: > Also: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Gerrit-Change-Number: 50286 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Feb 2021 08:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add chain-include list of headers
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: HAOUAS Elyes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50286 to look at the new patch set (#3). Change subject: Documentation: Add chain-include list of headers ...................................................................... Documentation: Add chain-include list of headers This list a non exhaustive intentionally indirect includes. Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A Documentation/chain-include.md 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50286/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Gerrit-Change-Number: 50286 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Add chain-include list of headers
by HAOUAS Elyes (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: HAOUAS Elyes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50286 to look at the new patch set (#2). Change subject: Documentation: Add chain-include list of headers ...................................................................... Documentation: Add chain-include list of headers This list a non exhaustive intentionally indirect includes. Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A Documentation/chain-include.md 1 file changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50286/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474d0d4bd660b62c24508bc3eba67154e820d8a4 Gerrit-Change-Number: 50286 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboards: Remove default CHROMEOS=y
by EricR Lai (Code Review) 05 Feb '21

05 Feb '21

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: mainboards: Remove default CHROMEOS=y ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Only amd/gizmo and google/peach_pit not have this flag. But looks like they never have this... -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Feb 2021 07:43:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Furquan Shaikh (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50299 ) Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 07:35:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
by chris wang (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Kevin Chiu, Felix Held. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust ...................................................................... Patch Set 13: (3 comments) File src/soc/amd/picasso/chip.h: https://review.coreboot.org/c/coreboot/+/50240/comment/cf90e072_233ad5cb PS7, Line 75: #define USB3_PORT_COUNT 4 > Yes, check with the design guide, the USB3 phy setting should only apply to controller 0. […] Done File src/soc/amd/picasso/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50240/comment/63312e1e_0a0ac299 PS4, Line 131: memcpy(&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0], : sizeof(scfg->usb_3_port0_phy_tune[0])); > yes, The default value was given in both trembyle and dalboz devtree. […] Done File src/vendorcode/amd/fsp/picasso/FspsUpd.h: https://review.coreboot.org/c/coreboot/+/50240/comment/cb75af72_c23f2363 PS7, Line 61: /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2]; > those port should belong to controller 0 and in our Picasso-PI or Pollock-PI. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 13 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Feb 2021 07:32:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: chris wang <Chris.Wang(a)amd.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Maulik V Vaghela (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50299 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... soc/intel/alderlake: Increase VBT size to 9 KiB Alderlake includes latest VBT (version 237 onwards),which has size of 8.5 KiB. This change is specific to alderlake so utilizing Kconfig option to increase VBT size specifically for ADL platforms. BUG=None BRANCH=None TEST=Include new VBT and boot the platform. Able to see firmware screen Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/50299/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Increase VBT size to 9 KiB
by Maulik V Vaghela (Code Review) 05 Feb '21

05 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50299 ) Change subject: soc/intel/alderlake: Increase VBT size to 9 KiB ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50299/comment/0ef0dea7_742bf28d PS2, Line 17: signed-off-by > No Signed-off-by line in commit message […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833 Gerrit-Change-Number: 50299 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 05 Feb 2021 07:23:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021